TAS2553_15 datasheet(14/58 Pages) TI

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8-BitDatafor

TAS2553

SLAS978B – SEPTEMBER 2013 – REVISED FEBRUARY 2014

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7.3 Feature Description

7.3.1 General I2C Operation

The TAS2553 operates as an I2C slave over the IOVDD voltage range. It is adjustable to one of two I2C

addresses. This allows two TAS2553 devices in a system to connect to the same I2C bus.

Set the ADDR terminal to ground to assign the device I2C address to 0x40 (7-bit). This is equivalent to 0x80 (8-

bit) for writing and 0x81 (8-bit) for reading.

Set ADDR to IOVDD for I2C address 0x41 (7-bit). This is equivalent to 0x82 (8-bit) for writing and 0x83 (8-bit) for

reading.

The I2C bus employs two signals, SDA (data) and SCL (clock), to communicate between integrated circuits in a

system. The bus transfers data serially, one bit at a time. The address and data 8-bit bytes are transferred most-

significant bit (MSB) first. In addition, each byte transferred on the bus is acknowledged by the receiving device

with an acknowledge bit. Each transfer operation begins with the master device driving a start condition on the

bus and ends with the master device driving a stop condition on the bus. The bus uses transitions on the data

terminal (SDA) while the clock is at logic high to indicate start and stop conditions. A high-to-low transition on

SDA indicates a start, and a low-to-high transition indicates a stop. Normal data-bit transitions must occur within

the low time of the clock period. Figure 23 shows a typical sequence.

The master generates the 7-bit slave address and the read/write (R/W) bit to open communication with another

device and then waits for an acknowledge condition. The TAS2553 holds SDA low during the acknowledge clock

period to indicate acknowledgment. When this occurs, the master transmits the next byte of the sequence. Each

device is addressed by a unique 7-bit slave address plus R/W bit (1 byte). All compatible devices share the same

signals via a bi-directional bus using a wired-AND connection.

Use external pull-up resistors for the SDA and SCL signals to set the logic-high level for the bus. Use pull-up

resistors between 660

Ω and 4.7 kΩ. Do not allow the SDA and SCL voltages to exceed the TAS2553 supply

voltage, IOVDD.

Figure 23. Typical I2C Sequence

There is no limit on the number of bytes that can be transmitted between start and stop conditions. When the last

word transfers, the master generates a stop condition to release the bus. Figure 23 shows a generic data

transfer sequence.

7.3.2 Single-Byte and Multiple-Byte Transfers

The serial control interface supports both single-byte and multiple-byte read/write operations for all registers.

During multiple-byte read operations, the TAS2553 responds with data, a byte at a time, starting at the register

assigned, as long as the master device continues to respond with acknowledges.

The TAS2553 supports sequential I2C addressing. For write transactions, if a register is issued followed by data

for that register and all the remaining registers that follow, a sequential I2C write transaction has taken place. For

I2C sequential write transactions, the register issued then serves as the starting point, and the amount of data

subsequently transmitted, before a stop or start is transmitted, determines to how many registers are written.

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