TAS2553_15 datasheet(23/58 Pages) TI

23 / 58 page

WCLK

BCLK

DOUT

DIN

td(DO-WS)

td(DO-BCLK)

tS(DI)

th(DI)

td(WS)

LD(n)

LD(n+1)

WORD

CLOCK

BIT

CLOCK

DATA

N N

RD(n)

LEFT CHANNEL

RIGHT CHANNEL

LD(n) = n'th sample of left channel data

RD(n) = n'th sample of right channel data

TAS2553

www.ti.com

SLAS978B – SEPTEMBER 2013 – REVISED FEBRUARY 2014

Device Functional Modes (continued)

Figure 36. Timing Diagram for I2S Mode with Offset=0 and Inverted Bit Clock

For I2S mode, the number of bit-clocks per channel should be greater than or equal to the programmed word-

length of the data. Also the programmed offset value should be less than the number of bit-clocks per frame by

at least the programmed word-length of the data.

7.4.1.4 Audio Data Serial Interface Timing (I2S, Left-Justified, Right-Justified Modes)

All specifications at 25°C, IOVDD = 1.8 V

NOTE

All timing specifications are measured at characterization but not tested at final test.

Figure 37. I2S/LJF/RJF Timing in Master Mode

Table 5. I2S/LJF/RJF Timing in Master Mode (see Figure 37)

IOVDD=1.8V

IOVDD=3.3V

PARAMETER

UNIT

MIN

MAX

MIN

MAX

td(WS)

WCLK delay

td(DO-WS)

WCLK to DOUT delay (For LJF Mode only)

td(DO-BCLK)

BCLK to DOUT delay

ts(DI)

DIN setup

th(DI)

DIN hold

Rise time

Fall time

Submit Documentation Feedback

Product Folder Links: TAS2553

TAS2553 数据表(PDF) 23 Page - Texas Instruments

TAS2553 数据表(HTML) 23 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58

数据表下载