TAS2553_15 datasheet(15/58 Pages) TI

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A0 R/W ACK A7

A0 ACK

ACK

Start

Condition

Stop

Condition

Acknowledge

I2CDeviceAddressand

Read/WriteBit

DataByte

D0 ACK

I2CDeviceAddressand

Read/WriteBit

Not

Acknowledge

R/W

RepeatStart

Condition

R/W ACK A7

A0 ACK

ACK

Start

Condition

Stop

Condition

Acknowledge

I2CDeviceAddressand

Read/WriteBit

DataByte

TAS2553

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SLAS978B – SEPTEMBER 2013 – REVISED FEBRUARY 2014

Feature Description (continued)

7.3.3 Single-Byte Write

As shown in Figure 24, a single-byte data-write transfer begins with the master device transmitting a start

condition followed by the I2C device address and the read/write bit. The read/write bit determines the direction of

the data transfer. For a write-data transfer, the read/write bit must be set to 0. After receiving the correct I2C

device address and the read/write bit, the TAS2553 responds with an acknowledge bit. Next, the master

transmits the register byte corresponding to the TAS2553 internal memory address being accessed. After

receiving the register byte, the TAS2553 again responds with an acknowledge bit. Finally, the master device

transmits a stop condition to complete the single-byte data-write transfer.

Figure 24. Single-Byte Write Transfer

7.3.4 Multiple-Byte Write and Incremental Multiple-Byte Write

A multiple-byte data write transfer is identical to a single-byte data write transfer except that multiple data bytes

are transmitted by the master device to the TAS2553 as shown in Figure 25. After receiving each data byte, the

TAS2553 responds with an acknowledge bit.

Figure 25. Multiple-Byte Write Transfer

7.3.5 Single-Byte Read

As shown in Figure 26, a single-byte data-read transfer begins with the master device transmitting a start

condition followed by the I2C device address and the read/write bit. For the data-read transfer, both a write

followed by a read are actually done. Initially, a write is done to transfer the address byte of the internal memory

address to be read. As a result, the read/write bit is set to a 0.

After receiving the TAS2553 address and the read/write bit, the TAS2553 responds with an acknowledge bit. The

master then sends the internal memory address byte, after which the TAS2553 issues an acknowledge bit. The

master device transmits another start condition followed by the TAS2553 address and the read/write bit again.

This time, the read/write bit is set to 1, indicating a read transfer. Next, the TAS2553 transmits the data byte from

the memory address being read. After receiving the data byte, the master device transmits a not-acknowledge

followed by a stop condition to complete the single-byte data read transfer.

The device address is 0x40 (7-bit). This is equivalent to 0x81 (8-bit) for reading.

Figure 26. Single-Byte Read Transfer

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