TAS2553_15 datasheet(30/58 Pages) TI

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DOUT

IVCLKIN

td(HI-Z)

DATA

HI-Z

td(DATA)

DATA

HI-Z

td(DATA)

DIN

IVCLKIN

DATA

DIN

IVCLKIN

DATA

TAS2553

SLAS978B – SEPTEMBER 2013 – REVISED FEBRUARY 2014

www.ti.com

Figure 47. DIN Timing Diagram in PDM Mode, Register 0x11, D(2) = 0

Figure 48. DIN Timing Diagram in PDM Mode, Register 0x11, D(2) = 1

Table 9. PDM Input Timing(1)

IOVDD=1.8V(2)

IOVDD=3.3V

PARAMETER

UNIT

MIN

MAX

MIN

MAX

DIN setup

DIN hold

Rise time

Fall time

(1)

All timing specifications are measured at characterization but not tested at final test.

(2)

All specifications at 25°C, IOVDD = 1.8 V

7.4.3.1 DOUT Timing – PDM Output Mode

Set Register 0x03, D(6) = 0 to transmit PDM data on the DOUT terminal. Register 0x07, D(7:6) selects either I

Data, V Data, or both for PDM transmission. Register 0x07, D(5) selects whether the data transmits on either the

rising edge or the falling edge of IVCLKIN. The DOUT terminal becomes high-impedance on the opposing clock

cycle.

Figure 49. DOUT Timing in PDM Mode (Data on IVCLKIN High)

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