PIC16F72SLASHML datasheet(24/136 Pages) MICROCHIP

24 / 136 page

PIC16F72

DS39597B-page 22

 2002 Microchip Technology Inc.

TABLE 3-1:

PORTA FUNCTIONS

TABLE 3-2:

SUMMARY OF REGISTERS ASSOCIATED WITH PORTA

Name

Bit#

Buffer

Function

RA0/AN0

bit 0

TTL

Input/output or analog input.

RA1/AN1

bit 1

TTL

Input/output or analog input.

RA2/AN2

bit 2

TTL

Input/output or analog input.

RA3/AN3/VREF

bit 3

TTL

Input/output or analog input or VREF.

RA4/T0CKI

bit 4

Input/output or external clock input for Timer0. Output is open drain type.

RA5/AN4/SS

bit 5

TTL

Input/output or analog input or slave select input for synchronous serial port.

Legend: TTL = TTL input, ST = Schmitt Trigger input

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Value on

POR, BOR

Value on

all other

RESETS

05h

PORTA

—

RA5

RA4

RA3

RA2

RA1

RA0

--0x 0000 --0u 0000

85h

TRISA

—

PORTA Data Direction Register

--11 1111 --11 1111

9Fh

ADCON1

—

PCFG2 PCFG1 PCFG0 ---- -000 ---- -000

Legend: x = unknown, u = unchanged, - = unimplemented locations read as ‘0’.

Shaded cells are not used by PORTA.

Note:

When using the SSP module in SPI Slave mode and SS enabled, the A/D Port Configuration Control bits

(PCFG2:PCFG0) in the A/D Control Register (ADCON1) must be set to one of the following configurations:

100, 101, 11x

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