PIC16F72SLASHML datasheet(70/136 Pages) MICROCHIP

70 / 136 page

PIC16F72

DS39597B-page 68

 2002 Microchip Technology Inc.

FIGURE 11-9:

SLOW RISE TIME (MCLR TIED TO VDD THROUGH RC NETWORK)

11.11 Interrupts

The PIC16F72 has up to eight sources of interrupt. The

interrupt control register (INTCON) records individual

interrupt requests in flag bits. It also has individual and

global interrupt enable bits.

A global interrupt enable bit, GIE (INTCON<7>)

enables (if set) all unmasked interrupts, or disables (if

cleared) all interrupts. When bit GIE is enabled, and an

interrupt’s flag bit and mask bit are set, the interrupt will

vector immediately. Individual interrupts can be dis-

abled through their corresponding enable bits in vari-

ous

registers.

Individual

interrupt

bits

are

set,

regardless of the status of the GIE bit. The GIE bit is

cleared on RESET.

The “return from interrupt” instruction, RETFIE, exits

the interrupt routine, as well as sets the GIE bit, which

re-enables interrupts.

The RB0/INT pin interrupt, the RB port change interrupt

and the TMR0 overflow interrupt flags are contained in

the INTCON register.

The peripheral interrupt flags are contained in the

Special Function Register, PIR1. The corresponding

interrupt enable bits are contained in Special Function

is contained in Special Function Register INTCON.

When an interrupt is serviced, the GIE bit is cleared to

disable any further interrupt, the return address is

pushed onto the stack, and the PC is loaded with

0004h. Once in the Interrupt Service Routine, the

source(s) of the interrupt can be determined by polling

the interrupt flag bits. The interrupt flag bit(s) must be

cleared in software before re-enabling interrupts to

avoid recursive interrupts.

For external interrupt events, such as the INT pin or

PORTB change interrupt, the interrupt latency will be

three or four instruction cycles. The exact latency

depends when the interrupt event occurs, relative to

the current Q cycle. The latency is the same for one or

two cycle instructions. Individual interrupt flag bits are

set, regardless of the status of their corresponding

mask bit, PEIE bit, or the GIE bit.

FIGURE 11-10:

INTERRUPT LOGIC

VDD

MCLR

INTERNAL POR

PWRT TIME-OUT

OST TIME-OUT

INTERNAL RESET

TPWRT

TOST

Note:

Individual interrupt flag bits are set, regard-

less of the status of their corresponding

mask bit, or the GIE bit.

ADIF

ADIE

SSPIF

SSPIE

CCP1IF

CCP1IE

TMR2IF

TMR2IE

TMR1IF

TMR1IE

TMR0IF

TMR0IE

INTF

INTE

RBIF

RBIE

GIE

PEIE

Wake-up (If in SLEEP mode)

Interrupt to CPU

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