PIC16F72SLASHML datasheet(9/136 Pages) MICROCHIP

9 / 136 page

 2002 Microchip Technology Inc.

DS39597B-page 7

PIC16F72

2.0

MEMORY ORGANIZATION

There are two memory blocks in the PIC16F72 device.

These are the program memory and the data memory.

Each block has separate buses so that concurrent

access can occur. Program memory and data memory

are explained in this section. Program memory can be

read internally by the user code (see Section 4.0).

The data memory can further be broken down into the

general purpose RAM and the Special Function

Registers (SFRs). The operation of the SFRs that

control the “core” are described here. The SFRs used

to control the peripheral modules are described in the

section discussing each individual peripheral module.

Additional information on device memory may be found

in the PICmicro™ Mid-Range Reference Manual,

(DS33023).

2.1

Program Memory Organization

PIC16F72 devices have a 13-bit program counter capa-

ble of addressing a 8K x 14 program memory space.

The address range for this program memory is 0000h -

07FFh. Accessing a location above the physically

implemented address will cause a wraparound.

The RESET Vector is at 0000h and the Interrupt Vector

is at 0004h.

FIGURE 2-1:

PROGRAM MEMORY MAP

AND STACK

2.2

Data Memory Organization

The Data Memory is partitioned into multiple banks that

contain the General Purpose Registers and the Special

Function Registers. Bits RP1 (STATUS<6>) and RP0

(STATUS<5>) are the bank select bits.

Each bank extends up to 7Fh (128 bytes). The lower

locations of each bank are reserved for the Special

Function Registers. Above the Special Function Regis-

ters are General Purpose Registers, implemented as

static RAM.

All implemented banks contain SFRs. Some “high use”

SFRs from one bank may be mirrored in another bank,

for code reduction and quicker access (e.g., the

STATUS register is in Banks 0 - 3).

2.2.1

GENERAL PURPOSE REGISTER

FILE

The register file can be accessed either directly, or indi-

rectly, through the File Select Register FSR (see

Section 2.5).

PC<12:0>

0000h

0004h

0005h

07FFh

1FFFh

Stack Level 1

Stack Level 8

RESET Vector

Interrupt Vector

On-chip Program

Memory

CALL, RETURN

RETFIE, RETLW

0800h

RP1:RP0

Bank

PIC16F72/ML 数据表(PDF) 9 Page - Microchip Technology

PIC16F72/ML 数据表(HTML) 9 Page - Microchip Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载