PIC16F72SLASHML datasheet(17/136 Pages) MICROCHIP

17 / 136 page

 2002 Microchip Technology Inc.

DS39597B-page 15

PIC16F72

2.2.2.4

PIE1 Register

This register contains the individual enable bits for the

peripheral interrupts.

PIE1: PERIPHERAL INTERRUPT ENABLE REGISTER 1 (ADDRESS 8Ch)

Note:

Bit PEIE (INTCON<6>) must be set to

enable any peripheral interrupt.

U-0

R/W-0

U-0

R/W-0

—

ADIE

—

SSPIE

CCP1IE

TMR2IE

TMR1IE

bit 7

bit 0

bit 7

Unimplemented: Read as ‘0’

bit 6

ADIE: A/D Converter Interrupt Enable bit

= Enables the A/D converter interrupt

= Disables the A/D converter interrupt

bit 5-4

Unimplemented: Read as ‘0’

bit 3

SSPIE: Synchronous Serial Port Interrupt Enable bit

= Enables the SSP interrupt

= Disables the SSP interrupt

bit 2

CCP1IE: CCP1 Interrupt Enable bit

= Enables the CCP1 interrupt

= Disables the CCP1 interrupt

bit 1

TMR2IE: TMR2 to PR2 Match Interrupt Enable bit

= Enables the TMR2 to PR2 match interrupt

= Disables the TMR2 to PR2 match interrupt

bit 0

TMR1IE: TMR1 Overflow Interrupt Enable bit

= Enables the TMR1 overflow interrupt

= Disables the TMR1 overflow interrupt

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

- n = Value at POR

‘1’ = Bit is set

‘0’ = Bit is cleared

x = Bit is unknown

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