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PIC16F72/ML 数据表(PDF) 56 Page - Microchip Technology |
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PIC16F72/ML 数据表(HTML) 56 Page - Microchip Technology |
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56 / 136 page  PIC16F72 DS39597B-page 54 2002 Microchip Technology Inc. REGISTER 10-2: ADCON1: A/D CONTROL REGISTER 1 (ADDRESS 9Fh) The ADRES register contains the result of the A/D con- version. When the A/D conversion is complete, the result is loaded into the ADRES register, the GO/DONE bit (ADCON0<2>) is cleared, and A/D interrupt flag bit ADIF is set. The block diagram of the A/D module is shown in Figure 10-1. The value in the ADRES register is not modified for a Power-on Reset. The ADRES register will contain unknown data after a Power-on Reset. After the A/D module has been configured as desired, the selected channel must be acquired before the con- version is started. The analog input channels must have their corresponding TRIS bits selected as an input. To determine acquisition time, see Section 10.1. After this acquisition time has elapsed, the A/D conversion can be started. The following steps should be followed for doing an A/D conversion: 1. Configure the A/D module: • Configure analog pins/voltage reference and digital I/O (ADCON1) • Select A/D input channel (ADCON0) • Select A/D conversion clock (ADCON0) • Turn on A/D module (ADCON0) 2. Configure A/D interrupt (if desired): • Clear ADIF bit • Set ADIE bit • Set GIE bit 3. Wait the required acquisition time. 4. Start conversion: • Set GO/DONE bit (ADCON0) 5. Wait for A/D conversion to complete, by either: • Polling for the GO/DONE bit to be cleared OR • Waiting for the A/D interrupt 6. Read A/D Result register (ADRES), clear bit ADIF if required. 7. For next conversion, go to step 1 or step 2 as required. The A/D conversion time per bit is defined as TAD. A minimum wait of 2 TAD is required before the next acquisition starts. U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 — — — — — PCFG2 PCFG1 PCFG0 bit 7 bit 0 bit 7-3 Unimplemented: Read as ‘0’ bit 2-0 PCFG<2:0>: A/D Port Configuration Control bits Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown A = Analog input D = Digital I/O PCFG2:PCFG0 RA0 RA1 RA2 RA5 RA3 VREF 000 AA A A A VDD 001 AA A A VREF RA3 010 AA A A A VDD 011 AA A A VREF RA3 100 AA D D A VDD 101 AA D D VREF RA3 11x DD D D D VDD |
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