PIC16F72SLASHML datasheet(66/136 Pages) MICROCHIP

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PIC16F72

DS39597B-page 64

 2002 Microchip Technology Inc.

11.5

Power-on Reset (POR)

A Power-on Reset pulse is generated on-chip when

VDD rise is detected (in the range of 1.2V - 1.7V). To

take advantage of the POR, tie the MCLR pin to VDD,

as described in Section 11.4. A maximum rise time for

VDD

specified.

See

Section 14.0,

Electrical

Characteristics for details.

When the device starts normal operation (exits the

RESET condition), device operating parameters (volt-

age, frequency, temperature,...) must be met to ensure

operation. If these conditions are not met, the device

must be held in RESET until the operating conditions

are met. For more information, see Application Note,

AN607- Power-up Trouble Shooting (DS00607).

11.6

Power-up Timer (PWRT)

The Power-up Timer provides a fixed 72 ms nominal

time-out on power-up only from the POR. The Power-

up Timer operates on an internal RC oscillator. The

chip is kept in RESET as long as the PWRT is active.

The PWRT’s time delay allows VDD to rise to an accept-

able level. A configuration bit is provided to enable/

disable the PWRT.

The power-up time delay will vary from chip to chip due

to VDD, temperature and process variation. See DC

parameters for details (TPWRT, parameter #33).

11.7

Oscillator Start-up Timer (OST)

The Oscillator Start-up Timer (OST) provides 1024

oscillator cycles (from OSC1 input) delay after the

PWRT delay is over (if enabled). This helps to ensure

that the crystal oscillator or resonator has started and

stabilized.

The OST time-out is invoked only for XT, LP and HS

modes and only on Power-on Reset or wake-up from

SLEEP.

11.8

Brown-out Reset (BOR)

The configuration bit, BOREN, can enable or disable

the Brown-out Reset circuit. If VDD falls below VBOR

(parameter D005, about 4V) for longer than TBOR

(parameter #35, about 100

µs), the brown-out situation

will reset the device. If VDD falls below VBOR for less

than TBOR, a RESET may not occur.

Once the brown-out occurs, the device will remain in

Brown-out Reset until VDD rises above VBOR. The

Power-up Timer then keeps the device in RESET for

TPWRT (parameter #33, about 72 ms). If VDD should fall

below VBOR during TPWRT, the Brown-out Reset pro-

cess will restart when VDD rises above VBOR, with the

Power-up Timer Reset. The Power-up Timer is always

enabled when the Brown-out Reset circuit is enabled,

regardless of the state of the PWRT configuration bit.

11.9

Time-out Sequence

On power-up, the time-out sequence is as follows: the

PWRT delay starts (if enabled) when a POR occurs.

Then, OST starts counting 1024 oscillator cycles when

PWRT ends (LP, XT, HS). When the OST ends, the

device comes out of RESET.

If MCLR is kept low long enough, all delays will expire.

Bringing MCLR high will begin execution immediately.

This is useful for testing purposes or to synchronize

more than one PIC16F72 device operating in parallel.

Table 11-5 shows the RESET conditions for the

STATUS, PCON and PC registers, while Table 11-6

shows the RESET conditions for all the registers.

11.10 Power Control/Status Register

(PCON)

The Power Control/Status Register, PCON, has two

bits to indicate the type of RESET that last occurred.

Bit0 is Brown-out Reset Status bit, BOR. Bit BOR is

unknown on a Power-on Reset. It must then be set by

the user and checked on subsequent RESETS to see

if bit BOR cleared, indicating a Brown-out Reset

occurred. When the Brown-out Reset is disabled, the

state of the BOR bit is unpredictable.

Bit1 is POR (Power-on Reset Status bit). It is cleared on

a Power-on Reset and unaffected otherwise. The user

must set this bit following a Power-on Reset.

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