PIC16F72SLASHML datasheet(37/136 Pages) MICROCHIP

37 / 136 page

 2002 Microchip Technology Inc.

DS39597B-page 35

PIC16F72

7.0

TIMER2 MODULE

The Timer2 module timer has the following features:

• 8-bit timer (TMR2 register)

• 8-bit period register (PR2)

• Readable and writable (both registers)

• Software programmable prescaler (1:1, 1:4, 1:16)

• Software programmable postscaler (1:1 to 1:16)

• Interrupt on TMR2 match of PR2

• SSP module optional use of TMR2 output to

generate clock shift

Timer2 has a control register, shown in Register 7-1.

Timer2 can be shut-off by clearing control bit TMR2ON

(T2CON<2>) to minimize power consumption.

Figure 7-1 is a simplified block diagram of the Timer2

module.

Additional information on timer modules is available in

the PICmicro™ Mid-Range MCU Reference Manual,

(DS33023).

7.1

Timer2 Operation

Timer2 can be used as the PWM time-base for PWM

mode of the CCP module.

The TMR2 register is readable and writable, and is

cleared on any device RESET.

The input clock (FOSC/4) has a prescale option of 1:1,

1:4

1:16,

selected

control

bits

T2CKPS1:T2CKPS0 (T2CON<1:0>).

The match output of TMR2 goes through a 4-bit

postscaler (which gives a 1:1 to 1:16 scaling inclusive)

to generate a TMR2 interrupt (latched in flag bit

TMR2IF, (PIR1<1>)).

7.2

Timer2 Prescaler and Postscaler

The prescaler and postscaler counters are cleared

when any of the following occurs:

• A write to the TMR2 register

• A write to the T2CON register

• Any device RESET (Power-on Reset, MCLR ,

WDT Reset, or Brown-out Reset)

TMR2 is not cleared when T2CON is written.

7.3

Timer2 Interrupt

The Timer2 module has an 8-bit period register, PR2.

Timer2 increments from 00h until it matches PR2 and

then resets to 00h on the next increment cycle. PR2 is

a readable and writable register. The PR2 register is

initialized to FFh upon RESET.

7.4

Output of TMR2

The output of TMR2 (before the postscaler) is fed to the

Synchronous Serial Port module, which optionally uses

it to generate a shift clock.

FIGURE 7-1:

TIMER2 BLOCK DIAGRAM

Comparator

TMR2

Sets Flag

TMR2 reg

Output(1)

RESET

Postscaler

Prescaler

PR2 reg

FOSC/4

1:1

1:16

1:1, 1:4, 1:16

bit TMR2IF

Note

1: TMR2 register output can be software

selected by the SSP module as a baud clock.

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