PIC16F72SLASHML datasheet(41/136 Pages) MICROCHIP

41 / 136 page

 2002 Microchip Technology Inc.

DS39597B-page 39

PIC16F72

8.2

Compare Mode

In Compare mode, the 16-bit CCPR1 register value is

constantly compared against the TMR1 register pair

value. When a match occurs, the RC2/CCP1 pin is:

• Driven High

• Driven Low

• Remains Unchanged

The action on the pin is based on the value of control

bits CCP1M3:CCP1M0 (CCP1CON<3:0>). At the

same time, interrupt flag bit CCP1IF is set.

The output may become inverted when the mode of the

module is changed from Compare/Clear on Match

(CCPxM<3:0> = ‘1001’) to Compare/Set on Match

(CCPxM<3:0> = ‘1000’). This may occur as a result of

any operation that selectively clears bit CCPxM0, such

as a BCF instruction.

When this condition occurs, the output becomes

inverted when the instruction is executed. It will remain

inverted for all following Compare operations, until the

module is reset.

FIGURE 8-2:

COMPARE MODE

OPERATION BLOCK

DIAGRAM

8.2.1

CCP PIN CONFIGURATION

The user must configure the RC2/CCP1 pin as an

output by clearing the TRISC<2> bit.

8.2.2

TIMER1 MODE SELECTION

Timer1 must be running in Timer mode or Synchro-

nized Counter mode, if the CCP module is using the

compare feature. In Asynchronous Counter mode, the

compare operation may not work.

8.2.3

SOFTWARE INTERRUPT MODE

When generate software interrupt is chosen, the CCP1

pin is not affected. Only a CCP interrupt is generated (if

enabled).

8.2.4

SPECIAL EVENT TRIGGER

In this mode, an internal hardware trigger is generated

that may be used to initiate an action.

The special event trigger output of CCP1 resets the

TMR1 register pair. This allows the CCPR1 register to

effectively be a 16-bit programmable period register for

Timer1.

The special trigger output of CCP1 resets the TMR1

module is enabled).

CCPR1H CCPR1L

TMR1H

TMR1L

Comparator

Output

Logic

Special Event Trigger

Set Flag bit CCP1IF

(PIR1<2>)

Match

RC2/CCP1

TRISC<2>

CCP1CON<3:0>

Mode Select

Output Enable

Special event trigger will:

•

RESET Timer1, but not set interrupt flag bit TMR1IF

(PIR1<0>)

•

Set bit GO/DONE (ADCON0<2>) bit, which starts an A/D

conversion

Note:

Clearing the CCP1CON register will force

the RC2/CCP1 compare output latch to the

default low level. This is not the data latch.

Note:

The special event trigger from the CCP1

module will not set interrupt flag bit

TMR1IF (PIR1<0>).

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