PIC16F72SLASHML datasheet(15/136 Pages) MICROCHIP

15 / 136 page

 2002 Microchip Technology Inc.

DS39597B-page 13

PIC16F72

2.2.2.2

OPTION Register

The OPTION register is a readable and writable regis-

ter that contains various control bits to configure the

TMR0 prescaler/WDT postscaler (single assignable

Interrupt, TMR0, and the weak pull-ups on PORTB.

OPTION REGISTER (ADDRESS 81h, 181h)

Note:

To achieve a 1:1 prescaler assignment for

the TMR0 register, assign the prescaler to

the Watchdog Timer.

R/W-1

RBPU

INTEDG

T0CS

T0SE

PSA

PS2

PS1

PS0

bit 7

bit 0

bit 7

RBPU: PORTB Pull-up Enable bit

= PORTB pull-ups are disabled

= PORTB pull-ups are enabled by individual port latch values

bit 6

INTEDG: Interrupt Edge Select bit

= Interrupt on rising edge of RB0/INT pin

= Interrupt on falling edge of RB0/INT pin

bit 5

T0CS: TMR0 Clock Source Select bit

= Transition on RA4/T0CKI pin

= Internal instruction cycle clock (CLKO)

bit 4

T0SE: TMR0 Source Edge Select bit

= Increment on high-to-low transition on RA4/T0CKI pin

= Increment on low-to-high transition on RA4/T0CKI pin

bit 3

PSA: Prescaler Assignment bit

= Prescaler is assigned to the WDT

= Prescaler is assigned to the Timer0 module

bit 2-0

PS2:PS0: Prescaler Rate Select bits

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

- n = Value at POR

‘1’ = Bit is set

‘0’ = Bit is cleared

x = Bit is unknown

000

001

010

011

100

101

110

111

1 : 2

1 : 4

1 : 8

1 : 16

1 : 32

1 : 64

1 : 128

1 : 256

1 : 1

1 : 2

1 : 4

1 : 8

1 : 16

1 : 32

1 : 64

1 : 128

Bit Value TMR0 Rate WDT Rate

PIC16F72/ML 数据表(PDF) 15 Page - Microchip Technology

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