PIC16F72SLASHML datasheet(98/136 Pages) MICROCHIP

98 / 136 page

PIC16F72

DS39597B-page 96

 2002 Microchip Technology Inc.

FIGURE 14-6:

RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP

TIMER TIMING

FIGURE 14-7:

BROWN-OUT RESET TIMING

TABLE 14-3:

RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER,

AND BROWN-OUT RESET REQUIREMENTS

VDD

MCLR

Internal

POR

PWRT

Time-out

OSC

Time-out

Internal

RESET

Watchdog

Timer

Reset

I/O Pins

Note: Refer to Figure 14-3 for load conditions.

VDD

VBOR

Parameter No. Symbol

Characteristic

Min

Typ†

Max

Units

Conditions

TmcL

MCLR Pulse Width (low)

——

µsVDD = 5V, -40°C to +85°C

31*

TWDT

Watchdog Timer Time-out Period

(No Prescaler)

718

VDD = 5V, -40°C to +85°C

TOST

Oscillation Start-up Timer Period

—

1024 TOSC

——

TOSC = OSC1 period

33*

TPWRT

Power-up Timer Period

132

VDD = 5V, -40°C to +85°C

TIOZ

I/O Hi-impedance from MCLR Low

or Watchdog Timer Reset

——

2.1

µs

TBOR

Brown-out Reset Pulse Width

100

——

µsVDD ≤ VBOR (D005)

* These parameters are characterized but not tested.

† Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested.

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