PIC16F72SLASHML datasheet(25/136 Pages) MICROCHIP

25 / 136 page

 2002 Microchip Technology Inc.

DS39597B-page 23

PIC16F72

3.2

PORTB and the TRISB Register

PORTB is an 8-bit wide, bi-directional port. The corre-

sponding data direction register is TRISB. Setting a

TRISB bit (= 1) will make the corresponding PORTB

pin an input (i.e., put the corresponding output driver in

a Hi-Impedance mode). Clearing a TRISB bit (= 0) will

make the corresponding PORTB pin an output (i.e., put

the contents of the output latch on the selected pin).

EXAMPLE 3-2:

INITIALIZING PORTB

Each of the PORTB pins has a weak internal pull-up. A

single control bit can turn on all the pull-ups. This is per-

formed by clearing bit RBPU (OPTION<7>). The weak

pull-up is automatically turned off when the port pin is

configured as an output. The pull-ups are disabled on a

Power-on Reset.

FIGURE 3-3:

BLOCK DIAGRAM OF

RB3:RB0 PINS

Four of PORTB’s pins, RB7:RB4, have an interrupt-on-

change feature. Only pins configured as inputs can

cause this interrupt to occur (i.e., any RB7:RB4 pin

configured as an output is excluded from the interrupt

on change comparison). The input pins (of RB7:RB4)

are compared with the old value latched on the last

read of PORTB. The “mismatch” outputs of RB7:RB4

are OR’d together to generate the RB Port Change

Interrupt with flag bit RBIF (INTCON<0>).

This interrupt can wake the device from SLEEP. The

user, in the Interrupt Service Routine, can clear the

interrupt in the following manner:

Any read or write of PORTB. This will end the

mismatch condition.

Clear flag bit RBIF.

A mismatch condition will continue to set flag bit RBIF.

Reading PORTB will end the mismatch condition and

allow flag bit RBIF to be cleared.

The interrupt-on-change feature is recommended for

wake-up on key depression operation and operations

where PORTB is only used for the interrupt-on-change

feature. Polling of PORTB is not recommended while

using the interrupt-on-change feature.

This interrupt-on-mismatch feature, together with soft-

ware configurable pull-ups on these four pins, allow

easy interface to a keypad and make it possible for

wake-up on key depression. Refer to the Embedded

Control Handbook, “Implementing Wake-Up on Key

Stroke” (AN552).

RB0/INT is an external interrupt input pin and is

configured using the INTEDG bit (OPTION<6>).

FIGURE 3-4:

BLOCK DIAGRAM OF

RB7:RB4 PINS

BANKSEL

PORTB

; Select bank for PORTB

CLRF

PORTB

; Initialize PORTB by

; clearing output

; data latches

BANKSEL

TRISB

; Select Bank for TRISB

MOVLW

0xCF

; Value used to

; initialize data

; direction

MOVWF

TRISB

; Set RB<3:0> as inputs

; RB<5:4> as outputs

; RB<7:6> as inputs

Data Latch

RBPU(1)

VDD

Data

RD TRIS

RD Port

Weak

Pull-up

RD Port

RB0/INT

I/O pin

TTL

Input

Buffer

Note 1: To enable weak pull-ups, set the appropriate TRIS bit(s)

Schmitt Trigger

Buffer

TRIS Latch

VDD

VSS

and clear the RBPU bit (OPTION<7>).

Bus

Port

TRIS

Data Latch

From Other

RBPU(1)

VDD

I/O pin

Data

Set RBIF

TRIS Latch

RD TRIS

RD Port

RB7:RB4 Pins

Weak

Pull-up

RD Port

Latch

TTL

Input

Buffer

Note 1: To enable weak pull-ups, set the appropriate TRIS bit(s)

Buffer

RB7:RB6 in Serial Programming Mode

VDD

VSS

and clear the RBPU bit (OPTION<7>).

Bus

Port

TRIS

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