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PIC16F72/ML 数据表(PDF) 39 Page - Microchip Technology |
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PIC16F72/ML 数据表(HTML) 39 Page - Microchip Technology |
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39 / 136 page ![]() 2002 Microchip Technology Inc. DS39597B-page 37 PIC16F72 8.0 CAPTURE/COMPARE/PWM (CCP) MODULE The CCP (Capture/Compare/PWM) module contains a 16-bit register that can operate as a: • 16-bit capture register • 16-bit compare register • PWM master/slave duty cycle register. Table 8-1 shows the timer resources of the CCP Module modes. Capture/Compare/PWM Register1 (CCPR1) is com- prised of two 8-bit registers: CCPR1L (low byte) and CCPR1H (high byte). The CCP1CON register controls the operation of CCP1. All are readable and writable. Additional information on the CCP module is available in the PICmicro™ Mid-Range MCU Reference Manual, (DS33023). TABLE 8-1: CCP MODE - TIMER RESOURCE REGISTER 8-1: CCPCON1: CAPTURE/COMPARE/PWM CONTROL REGISTER 1 (ADDRESS 17h) CCP Mode Timer Resource Capture Compare PWM Timer1 Timer1 Timer2 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — CCPxX CCPxY CCPxM3 CCPxM2 CCPxM1 CCPxM0 bit 7 bit 0 bit 7-6 Unimplemented: Read as '0' bit 5-4 CCPxX:CCPxY: PWM Least Significant bits Capture mode: Unused Compare mode: Unused PWM mode: These bits are the two LSbs of the PWM duty cycle. The eight MSbs are found in CCPRxL. bit 3-0 CCPxM3:CCPxM0: CCPx Mode Select bits 0000 = Capture/Compare/PWM disabled (resets CCPx module) 0100 = Capture mode, every falling edge 0101 = Capture mode, every rising edge 0110 = Capture mode, every 4th rising edge 0111 = Capture mode, every 16th rising edge 1000 = Compare mode, set output on match (CCPxIF bit is set) 1001 = Compare mode, clear output on match (CCPxIF bit is set) 1010 = Compare mode, generate software interrupt on match (CCPxIF bit is set, CCPx pin is unaffected) 1011 = Compare mode, trigger special event (CCPxIF bit is set, CCPx pin is unaffected); CCP1 resets TMR1 and starts an A/D conversion (if A/D module is enabled) 11xx = PWM mode Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown |
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