PIC16F72SLASHML datasheet(107/136 Pages) MICROCHIP

107 / 136 page

 2002 Microchip Technology Inc.

DS39597B-page 105

PIC16F72

FIGURE 14-16:

A/D CONVERSION TIMING

TABLE 14-10: A/D CONVERSION REQUIREMENTS

131

130

132

BSF ADCON0, GO

A/D CLK

A/D DATA

ADRES

ADIF

SAMPLE

OLD_DATA

SAMPLING STOPPED

DONE

NEW_DATA

(TOSC/2)(1)

432

Note

1: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the

SLEEP

instruction to be executed.

1 TCY

134

Param

No.

Sym

Characteristic

Min

Typ† Max Units

Conditions

130

TAD

A/D Clock Period

PIC16F72

1.6

——

µsTOSC based, VREF ≥ 3.0V

PIC16LF72

2.0

——

µsTOSC based,

2.0V

≤ VREF ≤ 5.5V

PIC16F72

2.0

4.0

6.0

µs A/D RC mode

PIC16LF72

3.0

6.0

9.0

µs A/D RC mode

131

TCNV

Conversion Time (not including S/H time)

(Note 1)

—

9TAD

132

TACQ

Acquisition Time

——

µs The minimum time is the

amplifier settling time. This

may be used if the “new”

input voltage has not

changed by more than 1 LSb

(i.e., 20.0 mV @ 5.12V) from

the last sampled voltage (as

stated on CHOLD).

134

TGO

Q4 to A/D Clock Start

—

TOSC/2

——

If the A/D clock source is

selected as RC, a time of TCY

is added before the A/D

clock starts. This allows the

SLEEP

instruction to be

executed.

These parameters are characterized but not tested.

†

Data in “Typ” column is at 5V, 25

°C unless otherwise stated. These parameters are for design guidance only

and are not tested.

Note 1: ADRES register may be read on the following TCY cycle.

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