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PC87413 数据表(PDF) 45 Page - National Semiconductor (TI) |
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PC87413 数据表(HTML) 45 Page - National Semiconductor (TI) |
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45 / 257 page  3.0 Device Architecture and Configuration (Continued) Revision 1.2 45 www.national.com Figure 5. Module Enable and Access Control 3.4 INTERNAL ADDRESS DECODING A full 16-bit address decoding is applied when accessing the configuration I/O space as well as the registers of the functional blocks. However, the number of configurable bits in the base address registers varies for each logical device. The lower 1, 2, 3, 4 or 5 address bits are decoded in the functional block to determine the offset of the accessed register within the logical device’s I/O range of 2, 4, 8, 16 or 32 bytes, respectively. The rest of the bits are matched with the base address register to decode the entire I/O range allocated to the logical device. Therefore, the lower bits of the base address register are forced to 0 (read only), and the base address is forced to be 2, 4, 8, 16 or 32 byte-aligned, according to the size of the I/O range. The base address of the FDC, Serial Port 1, Serial Port 2, KBC and RTC are limited to the I/O address range of 00h to 7FXh only (bits 11-15 are forced to 0). The Parallel Port base address is limited to the I/O address range of 00h to 3F8h. The addresses of the non-legacy logical devices, including the SWC, GPIO and X-Bus, are configurable within the full 16-bit ad- dress range (up to FFFXh). In some special cases, other address bits are used for internal decoding (such as bit 2 in the KBC and bit 10 in the Parallel Port). The KBC has two I/O base addresses with some implied dependency between them. For more details, see the de- scription of the base address register for each logical device. The X-Bus extension (PC87416 and PC87417) serves as a bridge from the LPC to the X-Bus. For module control and se- curity function registers, the 16-bit base address is applied through the configuration address space. The lower five address bits are decoded in the X-Bus to access each register. The address ranges in the LPC I/O space and the LPC or FWH mem- ory space that are bridged to the X-Bus are defined in the configuration section of the X-Bus bridge. The number of address bits used for this bridge decoding varies according to the specified zones and their sizes. See Sections 3.15.2 and 3.15.3 on pages 75ff. for details of the address range specifications. Access Lock LPC Bus Fast Disable xxxALOK ACCLCF2 Registers ACCLCF1, xxxDIS Register ACBFDIS Fast Disable xxxDIS Register SIOCF6 Fast Disable xxxDIS Register SWCFDIS Global Enable GLOBEN Register SIOCF1 Activation Bit Register Index 30h Device Configuration SWC Module ACCESS.bus Interface 01 Registers Runtime ACCESS.bus Module Enable Module (PC87413, PC87417) (PC87413, PC87417) |
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