PC87413 datasheet(76/257 Pages) NSC

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3.0 Device Architecture and Configuration (Continued)

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These decoded I/O zones are determined by the following seven registers: X-Bus I/O Configuration, X-Bus I/O Zone Base

Address 1/2 High and Low Byte and X-Bus I/O Size 1/2 Configuration. When a zone is enabled but is not associated with

any XCS0-3 select signal in the X-Bus Interface, the X-Bus does not respond to LPC transactions accessing that zone.

The I/O Address Map Lock bit (LOCKIOMP) in XIOCNF register enables protecting the contents of the I/O mapping by pre-

venting modifications to them that would cause access rights violation through aliasing.

Figure 7 illustrates the mapping of the User-Defined I/O zones to the host I/O space. The order between Base Address 1

and 2 is an example only and may be reversed.

3.15.3

X-Bus Memory Range Programming

LPC memory transactions or LPC-FWH transactions can be forwarded to the X-Bus Extension of the PC8741x device.

X-Bus Memory Configuration Register 1 defines the address space to which the device responds. The XCNF2 strap input

controls the default setting of the XMEMCNF1 register to enable booting from memories connected on the X-Bus. Two mem-

ory areas may be individually enabled: a user-defined zone and a BIOS memory zone (either BIOS-LPC, or BIOS-FWH

spaces).

To enable BIOS support, set the XCNF2 strap input to select the BIOS mode (see Section 1.4.11 on page 29 for details).

The PC8741x devices respond to LPC memory read and write transactions to/from the BIOS address spaces (see Table 28)

as long as the BIOLPCEN bit of XMEMCNF1 register is set (see Section 3.15.11 on page 83).

Table 28. BIOS-LPC Memory Space Deﬁnition

The PC8741x devices respond to LPC-FWH read transactions from the high memory address range (’386’ mode BIOS

range), shown in Table 28, as long as BIOFWHEN = 1 in the XMEMCNF1 register.

Memory Address Range

Description

000E 0000h - 000E FFFFh

Extended BIOS Range (Legacy)

Only when BIOEXTEN = 1 in XMEMCNF1 register

000F 0000h - 000F FFFFh

BIOS Range (Legacy)

FFFC 0000h - FFFF FFFFh

FFF8 0000h - FFFF FFFFh

FFF0 0000h - FFFF FFFFh

FFE0 0000h - FFFF FFFFh

FFC0 0000h - FFFF FFFFh

FF80 0000h - FFFF FFFFh

FF00 0000h - FFFF FFFFh

FE00 0000h - FFFF FFFFh

386 mode BIOS Range.

This is the upper 256 Kbytes to 32 Mbytes of the memory

space, depending on the setting of BIOSIZE and SEL2BIOS

in XMEMCNF2 (see Section 3.15.12 on page 84).

Figure 7. User-Deﬁned I/O Block Mapping

Host I/O Space

0000h

FFFFh

Base Address 1 (High, Low)

Base Address 2 (High, Low)

Zone Size 1

User-Deﬁned I/O Zone 2 (UDIZ2)

User-Deﬁned I/O Zone 3 (UDIZ3)

User-Deﬁned I/O Zone 0 (UDIZ0)

User-Deﬁned I/O Zone 1 (UDIZ1)

Zone Size 2

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