PC87413 datasheet(64/257 Pages) NSC

64 / 257 page

3.0 Device Architecture and Configuration (Continued)

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Revision1.2

3.10.3

Serial Port 2 Configuration Register

This register is reset by hardware to 02h.

Power Well:VDD

Location:Index F0h

Type:

R/W

Bit

76543210

Name

Bank

Select

Enable

Fast

TRI-STATE

Reserved

Busy

Indicator

Power

Mode

Control

TRI-STATE

Control

Reset

00000010

Bit

Description

Bank Select Enable. Enables bank switching for Serial Port 2.

0: All attempts to access the extended registers in Serial Port 2 are ignored (default)

1: Enables bank switching for Serial Port 2

Fast TRI-STATE. When set, the logical device output pins are in TRI-STATE and the input pins are internally

held at inactive level (high), regardless of the device activation (Activation bit - Section 3.3.1 on page 43;

SER2DIS - Section 3.7.7 on page 54; GLOBEN - Section 3.7.2 on page 49; SER2DIS - Section 9.3.8 on

page 185; SER2ALOK - Section 6.3.7 on page 132; SER2DIS - Section 6.3.5 on page 130).

0: Device pins active (default)

1: Device pins disabled

5-3

Reserved.

Busy Indicator. This read only bit can be used by power management software to decide when to power-down

the Serial Port 2 logical device.

0: No transfer in progress (default)

1: Transfer in progress

Power Mode Control. When the logical device is active in:

0: Low-Power mode

Serial Port 2 clock disabled. The output signals are set to their default states. The RI input signal can be pro-

grammed to generate an interrupt. Registers are maintained (unlike Active bit in index 30 that also prevents

access to Serial Port 2 registers).

1: Normal Power mode

Serial Port 2 clock enabled. Serial Port 2 is functional when the logical device is active (default).

TRI-STATE Control. When enabled and the device is inactive (see Section 3.3.1 on page 43), the logical device

output pins are in TRI-STATE.

0: Disabled (default)

1: Enabled

PC87413 数据表(PDF) 64 Page - National Semiconductor (TI)

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