PC87413 datasheet(79/257 Pages) NSC

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3.0 Device Architecture and Configuration (Continued)

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3.15.5

X-Bus I/O Base Address 1 High Byte Register (XIOBA1H)

This register describes the high byte of the Base Address for user-defined I/O zone blocks 0 and 1, which are mapped to

the X-Bus. This register is reset by hardware to 00h.

Power Well:VSB

Location:Index F1

Type:

R/W or RO

Bit

Type

Description

RW1L LOCKIOMP (Lock I/O Address Map). When set to 1, this bit locks the conﬁguration of registers

XIOCNF, XIOBA1H, XIOBA1L, XIOSIZE1, XIOBA2H, XIOBA2L and XIOSIZE2 by disabling writing to all

their bits (including to the LOCKIOMP bit itself). Once set, this bit can be cleared either by VDD Power-

Up reset (or Hardware reset) or by VSB Power-Up reset, according to the VSBLOCK bit in the

ACBLKCTL register (see Section 6.3.4 on page 128). In addition, this bit is cleared by setting the

UNLOCKX bit in the ACBLKCTL register (PC87417).

0: R/W bits are enabled for write (default)

1: All bits are RO

6-5

Reserved.

R/W or

TSTADEN (TST Debug Port Address Enable). When set, enables the mapping of I/O address 80h to

the X-Bus space.

0: Disabled (default)

1: Enabled

R/W or

UDIOZEN3 (User-Defined I/O Zone Enable 3). This bit enables the mapping of the User-Deﬁned I/O

zone 3 to the X-Bus space. The zone base address and size are deﬁned by the XIOBA2H/XIOBA2L

and XIOSIZE2 registers, respectively.

The base address for this Zone is: (Base Address 2) + (Size 2)

0: Disabled (default)

1: Enabled

R/W or

UDIOZEN2 (User-Defined I/O Zone Enable 2). This bit enables the mapping of the User-Deﬁned I/O

zone 2 to the X-Bus space. The zone base address and size are deﬁned by the XIOBA2H/XIOBA2L

and XIOSIZE2 registers, respectively.

The base address for this Zone is: (Base Address 2)

0: Disabled (default)

1: Enabled

R/W or

UDIOZEN1 (User-Defined I/O Zone Enable 1). This bit enables the mapping of the User-Deﬁned I/O

zone 1 to the X-Bus space. The zone base address and size are deﬁned by the XIOBA1H/XIOBA1L

and XIOSIZE1 registers, respectively.

The base address for this Zone is: (Base Address 1) + (Size 1)

0: Disabled (default)

1: Enabled

R/W or

UDIOZEN0 (User-Defined I/O Zone Enable 0). This bit enables the mapping of the User-Deﬁned I/O

zone 0 to the X-Bus space. The zone base address and size are deﬁned by the XIOBA1H/XIOBA1L

and XIOSIZE1 registers, respectively.

The base address for this Zone is: (Base Address 1)

0: Disabled (default)

1: Enabled

Bit

76543210

Name

IOBA1H

Reset

00000000

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