PC87413 datasheet(8/257 Pages) NSC

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Table of Contents (Continued)

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Revision 1.2

3.2.5

Default Configuration Setup ........................................................................................ 43

3.3

MODULE CONTROL ................................................................................................................. 43

3.3.1

Module Enable/Disable ................................................................................................ 43

3.3.2

Module Lock by ACCESS.bus (PC87413 and PC87417) ........................................... 44

3.4

INTERNAL ADDRESS DECODING .......................................................................................... 45

3.5

PROTECTION ........................................................................................................................... 46

3.5.1

Multiplexed Pins Configuration Lock ........................................................................... 46

3.5.2

GPIO Ports Configuration Lock ................................................................................... 46

3.5.3

Fast Disable Configuration Lock .................................................................................. 46

3.5.4

Clock Generator Configuration Lock ........................................................................... 46

3.5.5

GPIO Ports Lock .......................................................................................................... 46

3.5.6

X-Bus I/O Map Lock (PC87416 and PC87417) ........................................................... 47

3.5.7

X-Bus Memory Map Lock (PC87416 and PC87417) ................................................... 47

3.5.8

X-Bus Chip Select Configuration Lock (PC87416 and PC87417) ............................... 47

3.5.9

X-Bus Host Protection Lock (PC87416 and PC87417) ............................................... 47

3.5.10

SWC Timers Protection Lock ...................................................................................... 47

3.5.11

SWC Sleep State Configuration Lock .......................................................................... 47

3.5.12

CMOS RAM Access Lock ............................................................................................ 47

3.6

3.7

SERVERI/O CONFIGURATION REGISTERS .......................................................................... 48

3.7.1

ServerI/O ID Register (SID) ......................................................................................... 49

3.7.2

ServerI/O Configuration 1 Register (SIOCF1) ............................................................. 49

3.7.3

ServerI/O Configuration 2 Register (SIOCF2) ............................................................. 50

3.7.4

ServerI/O Configuration 3 Register (SIOCF3) ............................................................. 51

3.7.5

ServerI/O Configuration 4 Register (SIOCF4) ............................................................. 52

3.7.6

ServerI/O Configuration 5 Register (SIOCF5) ............................................................. 53

3.7.7

ServerI/O Configuration 6 Register (SIOCF6) ............................................................. 54

3.7.8

ServerI/O Revision ID Register (SRID) ....................................................................... 55

3.7.9

ServerI/O Configuration 8 Register (SIOCF8) ............................................................. 55

3.7.10

Clock Generator Configuration Register (CLOCKCF) ................................................. 56

3.7.11

ACCESS.bus Configuration (ACBCF) Register ........................................................... 57

3.8

FLOPPY DISK CONTROLLER (FDC) CONFIGURATION ........................................................ 58

3.8.1

General Description ..................................................................................................... 58

3.8.2

Logical Device 0 (FDC) Configuration ......................................................................... 58

3.8.3

FDC Configuration Register ........................................................................................ 59

3.8.4

Drive ID Register ......................................................................................................... 60

3.9

PARALLEL PORT (PP) CONFIGURATION ............................................................................. 61

3.9.1

General Description ..................................................................................................... 61

3.9.2

Logical Device 1 (PP) Configuration ............................................................................ 61

3.9.3

Parallel Port Configuration Register ............................................................................ 62

3.10

SERIAL PORT 2 CONFIGURATION ........................................................................................ 63

3.10.1

General Description ..................................................................................................... 63

3.10.2

Logical Device 2 (SP2) Configuration .......................................................................... 63

3.10.3

Serial Port 2 Configuration Register ............................................................................ 64

PC87413 数据表(PDF) 8 Page - National Semiconductor (TI)

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