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数据搜索系统，热门电子元器件搜索 |
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PC87413 数据表(PDF) 80 Page - National Semiconductor (TI) |
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PC87413 数据表(HTML) 80 Page - National Semiconductor (TI) |
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80 / 257 page  3.0 Device Architecture and Configuration (Continued) www.national.com 80 Revision1.2 3.15.6 X-Bus I/O Base Address 1 Low Byte Register (XIOBA1L) This register describes the low byte of the Base Address for User-Defined I/O zone blocks 0 and 1, which are mapped to the X-Bus. This register is reset by hardware to 00h. Power Well:VSB Location:Index F2h Type: R/W or RO 3.15.7 X-Bus I/O Size 1 Configuration Register (XIOSIZE1) This register defines the size of User-Defined I/O zone blocks 0 and 1, which are mapped to the X-Bus. The two blocks are contiguous and both have the same size. The User-Defined I/O Zone 1 address does not depend on Zone 0 being enabled. This register is reset by hardware to 00h. Power Well:VSB Location:Index F3h Type: R/W or RO Bit Description 7-0 IOBA1H (I/O User-Defined Zone Base Address 1 High). Defines the upper eight bits of the user-defined I/O blocks 0 and 1 base address. The base address must be aligned on the selected block size. Bit 76543210 Name IOBA1L Reset 00000000 Bit Description 7-0 IOBA1L (I/O User-Defined Zone Base Address 1 Low). Defines the lower eight bits of the user-defined I/O blocks 0 and 1 base address. The base address must be aligned on the selected block size. Bit 76543210 Name Reserved IOSIZE1 Reset 00000000 Bit Description 7-4 Reserved. 3-0 IOSIZE1 (User-Defined I/O Zone Size 1). Defines the size in bytes of the zone window. The size is defined as a power of two using the equation: NumOfBytes = 2n (where n = the value of the IOSIZE1 field). The zone must always be aligned to the window size (i.e., for a 128-byte window, the seven LSBs of the base address are zero). Bits 3 2 1 0 Size (Bytes) 0000: 1 (20 - default) ... 1 0 0 0: 256 (28) Other: Reserved |
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