PC87413 datasheet(88/257 Pages) NSC

88 / 257 page

3.0 Device Architecture and Configuration (Continued)

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Revision1.2

3.16.3

RAM Lock Register (RLR)

Once a non-reserved bit is set to 1, it can be cleared either by VDD Power-Up reset (or Hardware reset) or by VSB Power-Up

reset, according to the VSBLOCK bit in the ACBLKCTL register (see Section 6.3.4 on page 128). In addition, all the bits are

cleared by setting the UNLOCKR bit in the ACBLKCTL register (see Section 6.3.4 on page 128 - PC87413 and PC87417).

Power Well:VSB

Location:Index F0h

Type:

R/W1S

Bit

76543210

Name

BLSTR

BLRWR

BLEXRWR

BLEXRRD

BLEXR

Reserved

Reset

00000000

Bit

Description

BLSTR (Block Standard RAM). Disables both read and write access to locations 38h-3Fh of the Standard RAM

(writes are ignored; reads return FFh).

0: Normal access (default)

1: Read and write to locations 38h-3Fh of the Standard RAM are blocked

BLRWR (Block RAM Write). Disables write access to both the Standard and Extended RAM (writes are

ignored).

0: Normal access (default)

1: Writes to RAM (Standard and Extended) are blocked

BLEXRWR (Block Extended RAM Write). Disables write access to bytes 00h-1Fh of the Extended RAM (writes

are ignored).

0: Normal access (default)

1: Writes to bytes 00h-1Fh of the Extended RAM are blocked

BLEXRRD (Block Extended RAM Read). Disables read access from bytes 00h-1Fh of the Extended RAM

(reads return FFh).

0: Normal access (default)

1: Reads from bytes 00h-1Fh of the Extended RAM are blocked

BLEXR (Block Extended RAM). Disables both read and write access to the Extended RAM (writes are ignored;

reads return FFh).

0: Normal access (default)

1: Read and write to the Extended RAM are blocked

2-0

Reserved.

PC87413 数据表(PDF) 88 Page - National Semiconductor (TI)

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