PC87413 datasheet(96/257 Pages) NSC

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5.0 X-Bus Extension (Continued)

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Revision1.2

Figure 15. Mode 0, Normal Address X-Bus Transaction - Read Access Cycle

Write Transactions. When a write cycle on the LPC falls within any of the enabled decoded address ranges of the X-Bus

functional block (or an indirect write is started or an X-Bus write through the ACCESS.bus is started) and the relevant XCSn

is set to mode 0, a Mode 0 write cycle begins. A write cycle (see Figure 16) starts by outputting the address on address

signals XA11-0 and the data signals on data pins XD7-0 on the rising edge of the clock. One CLK cycle later, a chip-select

signal XCSn is asserted, where n is a chip-select number from 0 to 3, based on the address accessed and the select signal

mapping. Three CLK cycles later, on the rising edge of the clock, the XWR signal is asserted (set low), indicating a write

cycle and enabling the accessed device to be written. After 16 CLK cycles plus the internally programmed wait state period,

if XRDY use is enabled for this zone, its value is then sampled on the rising edge of the clock. The transaction is extended

until XRDY is detected to be high. Five CLK cycles later, XWR is de-asserted (set high) and one CLK cycle later, the trans-

action is completed by de-asserting XCSn and ﬂoating the data bus signals XD7-0. Two CLK cycles later, the address lines

are driven to 0.

CLK

(Internal; for

XD7-0

XA11-0

XCSn

XWR_XRW

Insert: 12 + “Programmed Wait States” CLK cycles here.

XRD_XEN

XRDY

XD7-0 (Data In)

(Data Read)

Reference Only)

During this time, non-clock signals do not change.

PC87413 数据表(PDF) 96 Page - National Semiconductor (TI)