PC87413 datasheet(73/257 Pages) NSC

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3.0 Device Architecture and Configuration (Continued)

Revision 1.2

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Table 26. Reset Values for PUPCTL Bit

Bit

Type

Description

Reserved (note that for Ports 0, 2, 3, 5, and 6, bits 7-4 are reserved).

R/W

Reserved for Ports 0, 2, 3, 5, and 6.

For Ports 1 and 4: EVDBNC (Event Debounce Enable). This bit enables the debounce circuit in the

event input path of the selected GPIO pin. The event is detected after a predetermined debouncing

period of time (see Section 7.3 on page 137).

0: Disabled

1: Enabled (default)

R/W

Reserved for Ports 0, 2, 3, 5, and 6.

For Ports 1 and 4: EVPOL (Event Polarity). This bit deﬁnes the polarity of the wake-up signal that

issues an event from the selected GPIO pin (see Section 7.3 on page 137).

0: Falling edge or low level input (default)

1: Rising edge or high level input

R/W

Reserved for Ports 0, 2, 3, 5, and 6.

For Ports 1 and 4: EVTYPE (Event Type). This bit deﬁnes the type of the wake-up signal that issues

an event from the selected GPIO pin (see Section 7.3 on page 137).

0: Edge input (default)

1: Level input

R/W1S LOCKCFP (Lock Configuration of Pin). When set to 1, this bit locks the GPIO pin conﬁguration and

data (see also Section 7.4 on page 139) by disabling writing to itself, to GPCFG1 register bits PUPCTL,

OUTTYPE and OUTENA, to all the bits of the GPCFG2 register and to the corresponding bit in the

GPDO register. Once set, this bit can be cleared by VDD Power-Up reset (or Hardware reset) or by VSB

Power-Up reset, according to the VSBLOCK bit in the ACBLKCTL register (see Section 6.3.4 on

page 128). In addition, this bit is cleared by setting the UNLOCKG bit in the ACBLKCTL register

(PC87413 and PC87417).

0: R/W bits are enabled for write (default)

1: All bits are RO

R/W or

PUPCTL (Pull-Up Control). This bit controls the internal pull-up resistor of the selected GPIO pin (see

Section 7.2 on page 136).

0: Disabled (for default value, see Table 26)

1: Enabled (for default value, see Table 26)

R/W or

OUTTYPE (Output Type). This bit controls the output buffer type of the selected GPIO pin (see Section

7.2 on page 136).

0: Open-drain (default)

1: Push-pull

R/W or

OUTENA (Output Enable). This bit controls the output buffer of the selected GPIO pin (see Section 7.2

on page 136).

0: TRI-STATE (default)

1: Output buffer enabled

GP(I)O(E)nn

00-07,10-17

20,21

22-25

26,27,30-37,40-42

43-47,50

51-53

54,55,60-63

641

1. The pull-up resistor is disabled during VSB Power-Up reset.

PUPCTL

101

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