PC87413 datasheet(77/257 Pages) NSC

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3.0 Device Architecture and Configuration (Continued)

Revision 1.2

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Table 29. BIOS-FWH Memory Space Deﬁnition

Upon reset in BIOS mode, both the BIOLPCEN and the BIOFWHEN bits in the XMEMCNF1 register are set. The PC8741x

device automatically detects the type of host boot protocol in use via the first completed BIOS read transaction after reset.

If the first read is an LPC memory read, the BIOFWHEN bit is cleared. If the first read is an LPC-FWH read, the BIOLPCEN

bit is cleared. The succeeding LPC or LPC-FWH transactions do not influence the BIOLPCEN and BIOFWHEN bits. The

software can later enable the response to both address spaces by setting the cleared bit. Figure 8 illustrates this behavior.

Figure 8. BIOS Mapping Enable Scheme

The two User-Defined Memory Zones (MEM0 and MEM1) are specified via a 32-bit base address. This address is formed

by eight bits of the XMEMBAL register, eight bits of the XMEMBAH register and 16 least significant bits of 0. The size of

each zone is specified through the XMEMSIZE register. The base address must be aligned to the block size. Figure 9 and

Figure 10 illustrate the mapping of the LPC and FWH spaces to the different memory zones.

The Memory Address Map Lock bit in X-Bus Memory Configuration Register 2 enables protection of the contents of the

memory mapping, thus preventing modifications to them that may cause access rights violation through aliasing.

The address used for the X-Bus transaction is the 28 least significant bits of the address bus. In read transactions, the data

read from the X-Bus is passed to the LPC bus. In write transactions, the data from the LPC is passed to the X-Bus.

Memory Address Range

Description

FFFC 0000h - FFFF FFFFh

FFF8 0000h - FFFF FFFFh

FFF0 0000h - FFFF FFFFh

FFE0 0000h - FFFF FFFFh

FFC0 0000h - FFFF FFFFh

FF80 0000h - FFFF FFFFh

FF00 0000h - FFFF FFFFh

FE00 0000h - FFFF FFFFh

386 mode BIOS Range.

This is the upper 256 Kbytes to 32 Mbytes of the memory

space, depending on the setting of BIOSIZE and SEL2BIOS

in XMEMCNF2 (see Section 3.15.12 on page 84). The

PC8741x devices use the ID field and address bits A18-A27

to A25-A27, respectively, to identify FWH access to the BIOS

memory.

Only hardware controlled transitions are shown.

Other transitions are possible via software

writing to the bits.

Note:

BIOFWHEN = 1

BIOLPCEN = 0

BIOFWHEN = 0

BIOLPCEN = 1

BIOFWHEN = 0

BIOLPCEN = 0

VSB Power-Up Reset

XCNF2 = Disable BIOS

XCNF2

= Enable

BIOS

First Memory Read

is LPC

First Memory Read

is FWH

BIOFWHEN = 1

BIOLPCEN = 1

PC87413 数据表(PDF) 77 Page - National Semiconductor (TI)

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