PC87413 datasheet(13/257 Pages) NSC

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Table of Contents (Continued)

Revision 1.2

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9.3.2

Wake-Up Event Select Register (WK_EVT_SEL) ..................................................... 178

9.3.3

Wake-Up State Enable Register (WK_ST_EN) ......................................................... 180

9.3.4

GPE1_STS Events to IRQ Enable Low Register (GPE1_2IRQ_LOW) ..................... 181

9.3.5

GPE1_STS Events to IRQ Enable High Register (GPE1_2IRQ_HIGH) ................... 182

9.3.6

GPE1_STS Events to SMI Enable Low Register (GPE1_2SMI_LOW) ..................... 183

9.3.7

GPE1_STS Events to SMI Enable High Register (GPE1_2SMI_HIGH) ................... 184

9.3.8

SWC Fast Disable Register (SWCFDIS) ................................................................... 185

9.3.9

SWC TRI-STATE Register (SWCTRIS) .................................................................... 186

9.3.10

SWC Miscellaneous Control Register (SWC_CTL) ................................................... 187

9.3.11

Power On Control Register (PWONCTL) .................................................................. 188

9.3.12

LED Control Register (LEDCTL) ............................................................................... 190

9.3.13

LED Blink Control Register (LEDBLNK) .................................................................... 191

9.3.14

BIOS General-Purpose Scratch Register (BIOSGPR) .............................................. 191

9.3.15

Bank Select Register (BANKSEL) ............................................................................. 192

9.3.16

Keyboard Wake-Up Control Register (KBDWKCTL) ................................................. 193

9.3.17

PS2 Protocol Control Register (PS2CTL) .................................................................. 194

9.3.18

Keyboard Data Shift Register (KDSR) ....................................................................... 195

9.3.19

Mouse Data Shift Register (MDSR) ........................................................................... 195

9.3.20

PS2 Keyboard Key Data 0 to 7 Registers (PS2KEY0 to PS2KEY7) ......................... 195

9.3.21

VDD Active Timer 0 Register (VDD_ON_TMR_0) .................................................... 196

9.3.22

VDD Active Timer 1 Register (VDD_ON_TMR_1) .................................................... 196

9.3.23

VDD Active Timer 2 Register (VDD_ON_TMR_2) .................................................... 196

9.3.24

VDD Active Timer 3 Register (VDD_ON_TMR_3) .................................................... 197

9.3.25

VSB Active Timer 0 Register (VSB_ON_TMR_0) ..................................................... 197

9.3.26

VSB Active Timer 1 Register (VSB_ON_TMR_1) ..................................................... 197

9.3.27

VSB Active Timer 2 Register (VSB_ON_TMR_2) ..................................................... 198

9.3.28

VSB Active Timer 3 Register (VSB_ON_TMR_3) ..................................................... 198

9.3.29

Power Active Timers Control Register (PWTMRCTL) ............................................... 199

9.3.30

S0 to S5 Sleep Type Encoding Registers (S0_SLP_TYP to S5_SLP_TYP) ............. 199

9.3.31

Sleep State Configuration Register (SLP_ST_CFG) ................................................. 200

9.3.32

ACPI Configuration Register (ACPI_CFG) ................................................................ 201

9.3.33

Watchdog Control Register (WDCTL) ....................................................................... 202

9.3.34

Watchdog Time-Out Register (WDTO) ...................................................................... 202

9.3.35

Watchdog Configuration Register (WDCFG) ............................................................. 203

9.4

ACPI REGISTERS ................................................................................................................... 204

9.4.1

ACPI Register Map .................................................................................................... 204

9.4.2

PM1 Status Low Register (PM1b_STS_LOW) .......................................................... 205

9.4.3

PM1 Status High Register (PM1b_STS_HIGH) ........................................................ 205

9.4.4

PM1 Enable Low Register (PM1b_EN_LOW) ........................................................... 206

9.4.5

PM1 Enable High Register (PM1b_EN_HIGH) ......................................................... 207

9.4.6

PM1 Control Low Register (PM1b_CNT_LOW) ........................................................ 208

9.4.7

PM1 Control High Register (PM1b_CNT_HIGH) ....................................................... 208

9.4.8

General-Purpose Status 1 Register 0 (GPE1_STS_0) .............................................. 209

9.4.9

General-Purpose Status 1 Register 1 (GPE1_STS_1) .............................................. 209

9.4.10

General-Purpose Status 1 Register 2 (GPE1_STS_2) .............................................. 210

9.4.11

General-Purpose Status 1 Register 3 (GPE1_STS_3) .............................................. 211

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