PC87413 datasheet(90/257 Pages) NSC

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Revision 1.2

4.0

LPC Bus Interface

With the exception of the ACCESS.bus Interface, the host can access all the functional blocks of the PC8741x device

through the LPC bus.

4.1

OVERVIEW

The LPC host Interface supports 8-bit I/O Read, 8-bit I/O Write and 8-bit DMA transactions, as defined in Intel’s LPC Inter-

face Speciﬁcation, Revision 1.0.

4.2

LPC TRANSACTIONS

The LPC Interface of the PC8741x devices can respond to the following LPC transactions as part of the standard ServerI/O

implementation:

• 8-bit I/O read and write cycles.

• 8-bit DMA read and write cycles.

• DMA request cycles.

In addition, the X-Bus bridge uses the following transactions (PC87416 and PC87417):

• 8-bit I/O read and write cycles.

• 8-bit memory read and write.

• 8-bit FWH read

LPC-FWH Cycles: The LPC bus and the ACCESS.bus (PC87413 and PC87417) use the internal bus of the PC8741x de-

vice to access the internal modules or to bridge transactions to the X-Bus (see the Block Diagrams on pages 1 and 5). In

case both the LPC and the ACCESS.bus try to access targets (same or different) through the internal bus simultaneously,

the LPC transaction is deferred until the end of the ACCESS.bus transaction. This is achieved by generating Long Wait

SYNC cycles on the LPC bus. The amount of time the LPC bus waits depends on the duration of the ACCESS.bus transac-

tion (see Section 6.2.10 on page 125). An LPC transaction that starts before an ACCESS.bus transaction is performed nor-

mally (i.e., without interference).

The LPC-FWH read cycle is similar to the LPC memory read cycle, as shown below. The DATA, TAR and SYNC fields are

as specified for LPC memory read cycle. The START field is similar to the equivalent field in the LPC memory read cycle

but differs in the data placed on the LAD signals (see details in the cycle description). The Address field contains only seven

nibbles (A27-A0), starting with the most significant. The IDSEL and MSIZE fields are specific to LPC-FWH transactions.

FWH Read Cycle

1. START

FWH Memory Read cycle type = 1101 (0Dh).

2. IDSEL

FWH Device Select ID nibble (compared with the FWHID field in the XMEMCNF1 register,

Section 3.15.11 on page 83).

3. MADDR

Memory Address: seven address nibbles, MS nibble first (see LPC-FWH Address Translation:, below).

4. MSIZE

Memory Size, single byte = 0000 (00h).

5. TAR (two cycles).

6. SYNC.

7. DATA

Data: two nibbles, LS nibble first (D3-D0, D7-D4).

8. TAR (two cycles).

The IDSEL field is compared with the FWHID field in the XMEMCNF1 register, as described in Section 3.15.11 on page 83.

If the two match, the PC8741x device continues handling the transaction; if not, the current LPC-FWH transaction is ignored.

The MSIZE field is ignored by the PC8741x devices.

LPC-FWH Address Translation: The address field in the LPC-FWH transaction is constructed of seven nibbles, containing

the 28 LS address bits (A27-A0), as follows: the first incoming nibble corresponds to addresses A27-A24, the second to A23-

A20, and so forth, until the seventh nibble, which corresponds to A3-A0. The MS bits of the 32-bit addresses (A31-A28) are

assumed to be ‘1111’.

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