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数据搜索系统，热门电子元器件搜索 |
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PC87413 数据表(PDF) 74 Page - National Semiconductor (TI) |
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PC87413 数据表(HTML) 74 Page - National Semiconductor (TI) |
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74 / 257 page  3.0 Device Architecture and Configuration (Continued) www.national.com 74 Revision1.2 3.14.5 GPIO Event Routing Register (GPEVR) This register enables the routing of the GPIO event (see Section 7.3.2 on page 138) to IRQ and/or SIOSMI signals. It is implemented only for Ports 1 and 4, which have wake-up event detection capability. This register is reset by hardware to 01h. Power Well:VSB Location:Index F2h Type: R/W 3.14.6 GPIO Pin Configuration Register 2 (GPCFG2) This register controls the access to the GPIO pin from one of the two buses. This register is reset by hardware to 00h. Power Well:VSB Location:Index F3h Type: R/W or RO Bit 76543210 Name Reserved EV2SMI EV2IRQ Reset 00000001 Bit Description 7-2 Reserved. 1 EV2SMI (Event to SMI Routing). Controls the routing of the event from the selected GPIO pin to SIOSMI (see Section 7.3 on page 137). 0: Disabled (default) 1: Enabled 0 EV2IRQ (Event to IRQ Routing). Controls the routing of the event from the selected GPIO pin to IRQ (see Section 7.3 on page 137). 0: Disabled 1: Enabled (default) Bit 76543210 Name Reserved BUSCTL VDDLOAD Reserved Reset 00000000 Bit Description 7 Reserved. 6-5 BUSCTL (Bus Control). These bits select the bus (ACCESS.bus or LPC bus) that controls the configuration and data of the selected GPIO pin. The bus not selected has read-only access to the GPCFG1, GPCFG2 and GPEVR registers and to the corresponding bit in the GPDO, GPEVEN and GPEVST registers (see Section 7.4.2 on page 140). In the PC87414 and PC87416, these bits are irrelevant because only the LPC bus is available. Bits 6 5 Function 0 0: Access from ACCESS.bus and LPC bus (default) 0 1: Access from ACCESS.bus only 1 0: Access from LPC bus only 1 1: Reserved 4 VDDLOAD (VDD-Powered Load). This bit indicates that the selected GPIO pin is connected to a device powered by VDD. The input and output (including the internal pull-up) of such a GPIO pin are disabled whenever VDD power to the PC8741x device falls below a certain value (see Section 11.1.5 on page 232). 0: GPIO pin connected to a VSB-powered load (default) 1: GPIO pin connected to a VDD-powered load 3-0 Reserved. |
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