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PC87413 数据表(PDF) 97 Page - National Semiconductor (TI) |
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PC87413 数据表(HTML) 97 Page - National Semiconductor (TI) |
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97 / 257 page  5.0 X-Bus Extension (Continued) Revision 1.2 97 www.national.com Figure 16. Mode 0, Normal Address X-Bus Transaction - Write Access Cycle 5.2.6 Mode 0, Normal Address, Fast X-Bus Transactions The read and write transactions in Normal Address, Fast X-Bus transactions are similar to those in Mode 0, Normal Address X-Bus Transactions on page 95, differing only in the delay for valid data. Because Normal Address, Fast X-Bus transactions have 14 to 20 fewer cycles than Normal Address transactions, they can be used to speed up access to fast devices. The gray areas in Figures Figure 15 and Figure 16 (+ 2 CLK cycles) represent the additional cycles that Fast transactions (Fig- ures Figure 17 and Figure 18) do not perform. This mode is selected for transactions accessing XCSn by setting TRANSMD = 0 and TRANSPD = 1 in the corresponding XZMn register. CLK (Internal; XD7-0 XA11-0 XCSn XWR_XRW Insert: 12 + “Programmed Wait States” CLK cycles here. During this time, non-clock signals do not change. XRD_XEN XRDY for Reference Only) |
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