PC87413 datasheet(49/257 Pages) NSC

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3.0 Device Architecture and Configuration (Continued)

Revision 1.2

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3.7.1

ServerI/O ID Register (SID)

This register contains the identity number of the device family. The PC8741x family is identified by the value EEh.

Power Well:VSB

Location:Index 20h

Type:

3.7.2

ServerI/O Configuration 1 Register (SIOCF1)

Power Well:VSB

Location:Index 21h

Type:

Varies per bit

Bit

76543210

Name

Family ID

Reset

EEh

Bit

Description

7-0

Family ID. These bits identify a family of devices with similar functionality but with different implemented

options.

Bit

43210

Name

LOCKMCF

LOCKGCF

Reserved

IOWAIT

HSWRST

GLOBEN

Reset

10001

Bit

Type

Description

R/W1S LOCKMCF (Lock Multiplexing Configuration). When set to 1, this bit locks the conﬁguration of

registers SIOCF1, SIOCF2, SIOCF3, SIOCF4 and SIOCF5 by disabling writing to all bits in these

registers (including the LOCKMCF bit itself), except for the LOCKGCF, HSWRST and GLOBEN bits of

SIOCF1. Once set, this bit can be cleared either by VDD Power-Up reset (or Hardware reset) or by VSB

Power-Up reset, according to the VSBLOCK bit in the ACBLKCTL register (see Section 6.3.4 on

page 128). In addition, this bit is cleared by setting the UNLOCKM bit in the ACBLKCTL register

(PC87413 and PC787417).

0: R/W bits are enabled for write (default)

1: All bits are RO

R/W1S LOCKGCF (Lock GPIO Pins Configuration). When set to 1, this bit locks the conﬁguration registers

of all the GPIO pins (see Section 3.14.2 on page 71) by disabling writing to all their bits (including the

LOCKGCF bit itself). Once set, this bit can be cleared either by VDD Power-Up reset (or Hardware

reset) or by VSB Power-Up reset, according to the VSBLOCK bit in the ACBLKCTL register (see

Section 6.3.4 on page 128). In addition, this bit is cleared by setting the UNLOCKG bit in the

ACBLKCTL register

(PC87413 and PC787417).

0: R/W bits are enabled for write (default)

1: All bits are RO

5-4

Reserved (must be ‘01’).

3-2

R/W or

IOWAIT (Number of I/O Wait States). These bits set the number of wait states for I/O transactions

through the LPC bus.

Bits

3 2

Number of wait states

0 0:

0 (Zero - default)

0 1:

1 0:

1 1:

PC87413 数据表(PDF) 49 Page - National Semiconductor (TI)

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