PC87413 datasheet(70/257 Pages) NSC

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3.0 Device Architecture and Configuration (Continued)

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Revision1.2

3.14 GENERAL-PURPOSE INPUT/OUTPUT (GPIO) PORTS CONFIGURATION

3.14.1

General Description

The GPIO functional block includes 51 pins arranged in seven ports:

Ports 1 and 4 contain eight GPIOE pins each.

Ports 0, 2 and 3 contain eight GPIO pins each.

Port 5 contains six GPIO pins.

Port 6 contains ﬁve GPO pins (see Section 1.4.8 on page 27).

All the pins of Ports 1 and 4 and have full event detection capability (see Section 1.3 on page 20), enabling them to trigger

the assertion of IRQ or SIOSMI signals. In addition, through the SWC functional block, the pins of Ports 1 and 4 can trigger

the SIOSCI, control the ONCTL signal or enable the generation of a pulse in the PWBTOUT signal. The pins of Ports 0-5

are I/O, however the five pins of Port 6 are output only.

All 51 GPIO pins are powered from the VSB well. The 17 runtime registers associated with the seven ports are arranged in

the GPIO address space as shown in Table 24. The GPIO ports with wake-up event detection capability (such as Ports 1

and 4) have four runtime registers; the other ports have only 2. Port 6 contains only GPO pins and therefore has only one

runtime register. The GPIO base address is 32-byte aligned. Address bits 4-0 are used to indicate the register offset.

The specific runtime registers implemented in the PC8741x devices are shown in Table 24. All these registers are VSB pow-

ered.

Table 24. Runtime Registers in GPIO Address Space

Offset

Mnemonic

Port Power Well

Type

00h

GPDO0

GPIO Data Out 0

0VSB

R/W

01h

GPDI0

GPIO Data In 0

VSB

02h

GPDO1

GPIO Data Out 1

1VSB

R/W

03h

GPDI1

GPIO Data In 1

VSB

04h

GPEVEN1 GPIO Event Enable 1

VSB

R/W

05h

GPEVST1 GPIO Event Status 1

VSB

R/W1C

06h

GPDO2

GPIO Data Out 2

2VSB

R/W

07h

GPDI2

GPIO Data In 2

VSB

08h

GPDO3

GPIO Data Out 3

3VSB

R/W

09h

GPDI3

GPIO Data In 3

VSB

0Ah

GPDO4

GPIO Data Out 4

4VSB

R/W

0Bh

GPDI4

GPIO Data In 4

VSB

0Ch

GPEVEN4 GPIO Event Enable 4

VSB

R/W

0Dh

GPEVST4 GPIO Event Status 4

VSB

R/W1C

0Eh

GPDO5

GPIO Data Out 5

5VSB

R/W

0Fh

GPDI5

GPIO Data In 5

VSB

10h

GPDO6

GPIO Data Out 6

6VSB

R/W

PC87413 数据表(PDF) 70 Page - National Semiconductor (TI)

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