PC87413 datasheet(95/257 Pages) NSC

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5.0 X-Bus Extension (Continued)

Revision 1.2

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5.2.4

Indirect Memory Read and Write Transactions

I/O mapped registers accessed through an LPC I/O transaction may be used to perform an X-Bus memory transaction. This

mechanism uses the following X-Bus Extension module registers:

Four Indirect Memory Address registers (XIMA3-0), representing address bits 31 to 0.

One Indirect Memory Data register (XIMD), representing data bits 7 to 0.

Four enable bits, one for each Select Conﬁguration register, XZCNF0, XZCNF1, XZCNF2 and XZCNF3.

Following an LPC I/O write to the XIMD register, a Memory write cycle is initiated on the X-Bus using the addresses from

the previously written XIMA3-0 registers and data from the XIMD register. Following an LPC I/O read from the XIMD register,

a Memory read cycle is initiated on the X-Bus using the address from the XIMA3-0 registers. The returned data from the X-

Bus cycle is used to finish the read cycle from the XIMD register.

Indirect memory transactions may be enabled for one chip-select signal only. If more than one enable bit in the Select Con-

ﬁguration registers is set, the indirect memory access will be available only for the XCSn with the highest priority. The setting

of the enable bit for the chip selects with lower priority will be ignored. XCS0 has the highest priority and XCS3 has the lowest

priority.

5.2.5

Mode 0, Normal Address X-Bus Transactions

The read and write transactions in Normal Address mode are similar to those used in the X-Bus or ISA bus. At least two idle

cycles are inserted at the end of each X-Bus transaction cycle before the next transaction starts (there may be more idle

cycles due to the LPC transactions). This mode is selected for transactions accessing XCSn by setting TRANSMD = 0 in the

corresponding XZMn register.

Read Transactions. When a read cycle on the LPC falls within an enabled decoded address range of the X-Bus functional

block (or an indirect read is started or an X-Bus read through the ACCESS.bus is started) and the relevant XCSn is set to

mode 0, a Mode 0 read cycle begins. A read cycle (see Figure 15) starts by outputting the address on address signals XA11-

0 on the rising edge of the clock. During this time, the PC8741x device does not drive the data bus signals XD7-0. One CLK

cycle later, a chip-select signal XCSn is asserted, where n is a chip-select number from 0 to 3, based on the address ac-

cessed and the select signal mapping. Three CLK cycles later, on the rising edge of the clock, the XRD signal is asserted

(set low), indicating a read cycle and enabling the accessed device to drive the data bus. After 16 CLK cycles plus the inter-

nally programmed wait state period, if XRDY use is enabled for this zone, its value is then sampled on the rising edge of the

clock. The transaction is extended until XRDY is detected to be high. Four CLK cycles later, the input data XD7-0 is sampled

on the rising edge of the clock. One CLK cycle later, XRD is de-asserted (set high) and one CLK cycle after that, the trans-

action is completed by de-asserting XCSn. The address is retained for two more CLK cycles after which the address lines

are driven to 0.

PC87413 数据表(PDF) 95 Page - National Semiconductor (TI)

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