| 数据搜索系统,热门电子元器件搜索 |
|
ST7MC1 数据表(PDF) 174 Page - STMicroelectronics |
|
|
|||||||||||||||||||||||||||||
ST7MC1 数据表(HTML) 174 Page - STMicroelectronics |
|
174 / 308 page ![]() ST7MC1/ST7MC2 174/308 MOTOR CONTROLLER (Cont’d) 10.6.7.4 Built-in Checks and Controls for simulated events As described in Figure 91. on page 167, MZREG, MDREG and MCOMP registers are capture/com- pare registers. The Compare registers are write accessible and can be used to generate simulated events. The value of the MTIM timer is compared with the value written in the registers and when the MTIM value reaches the corresponding register value, the simulated event is generated. Simulated event generation is enabled when the correspond- ing bits are set: – In the MCRB register for simulated demagneti- sation – SDM for simulated demagnetisation – In the MCRC register for simulated zero-crossing and commutation. – SC for simulated commutation – SZ for simulated zero-crossing event. To avoid a system stop, special attention is need- ed when writing in the register to generate the cor- responding simulated event. The value written in the register has to be greater than the current val- ue of the MTIM timer when writing in the registers. If the value written in the registers (MDREG, MZREG or MCOMP) is already less than the cur- rent value of MTIM, the simulated event will never be generated and the system will be stopped. For this reason, built-in checks and controls have been implemented in the MTIM timer. If the value written in one of those registers in sim- ulated event generation mode is less than or equal to the current value of the timer when it is com- pared, the simulated event is generated immedi- ately and the value of the MTIM timer at the time the simulated event occurs overwrites the value in the registers. Like that the value in the register re- ally corresponds to the simulated event generation and can be re-used to generate the next simulated event. So, the value written in the registers able to gener- ate simulated events is checked by hardware and compare to the current MTIM value to verify that it is greater. Figure 95. Simulated demagnetisation / zero-crossing event generation (SC=0) CH CH CH ZH DS During C interrupt Simulated or Hardware D/Z events Value written in MDREG/MZREG if simulated event generation DH ZH DS ZS ZS After C interrupt MDREG value checked if MDREG<=MTIM Immediate DS generation After D interrupt MZREG value checked if MZREG<=MTIM Immediate ZS generation ZS Simulated zero-crossing DS Simulated demagnetisation ZH Hardware zero-crossing CH Hardware commutation t 1 |
|
链接网址 |
| ALLDATASHEET是否为您带来帮助? [ DONATE ] |
关于 Alldatasheet | 广告服务 | 联系我们 | 隐私政策 | 数据表链接 | 链接交换 | 制造商名单 All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |