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ST72734 数据表(PDF) 113 Page - STMicroelectronics |
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ST72734 数据表(HTML) 113 Page - STMicroelectronics |
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113 / 144 page ![]() ST72774/ST727754/ST72734 113/144 DDC INTERFACE (Cont’d) DDC DATA REGISTER (DR) Read / Write Reset Value: 0000 0000 (00h) Bit 7:0 = D7-D0 8-bit Data Register. These bits contain the byte to be received or transmitted on the bus. – Transmitter mode: Byte transmission start auto- matically when the software writes in the DR reg- ister. – Receiver mode: the first data byte is received au- tomatically in the DR register using the least sig- nificant bit of the address. Then, the next data bytes are received one by one after reading the DR register. DDC OWN ADDRESS REGISTER (OAR) Read / Write Reset Value: 0000 0000 (00h) Bit 7:1 = ADD7-ADD1 Interface address. These bits define the I2C bus programmable address of the interface. They are not cleared when the interface is disabled (PE=0). Bit 0 = ADD0 . This bit is Don’t Care, the interface acknowledges either 0 or 1. It is not cleared when the interface is disabled (PE=0). Note: Address 01h is always ignored. 70 D7 D6 D5 D4 D3 D2 D1 D0 70 ADD7 ADD6 ADD5 ADD4 ADD3 ADD2 ADD1 ADD0 |
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