ST72734 datasheet(112/144 Pages) STMICROELECTRONICS

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ST72774/ST727754/ST72734

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DDC INTERFACE (Cont’d)

DDC STATUS REGISTER 2 (SR2)

Read Only

Reset Value: 0000 0000 (00h)

Bit 7:5 = Reserved. Forced to 0 by hardware.

Bit 4 = AF

Acknowledge failure.

This bit is set by hardware when no acknowledge

is returned. An interrupt is generated if ITE=1. It is

cleared by software reading SR2 register or by

hardware when the interface is disabled (PE=0).

The SCL line is not held low while AF=1.

0: No acknowledge failure

1: Acknowledge failure

Bit 3 = STOPF

Stop detection.

This bit is set by hardware when a Stop condition is

detected on the bus after an acknowledge (if

ACK=1). An interrupt is generated if ITE=1. It is

cleared by software reading SR2 register or by

hardware when the interface is disabled (PE=0).

The SCL line is not held low while STOPF=1.

0: No Stop condition detected

1: Stop condition detected

Bit 2 = Reserved. Forced to 0 by hardware.

Bit 1 = BERR

Bus error.

This bit is set by hardware when the interface

detects a misplaced Start or Stop condition. An

interrupt is generated if ITE=1. It is cleared by

software reading SR2 register or by hardware

when the interface is disabled (PE=0).

The SCL line is not held low while BERR=1.

0: No misplaced Start or Stop condition

1: Misplaced Start or Stop condition

Bit 0 = EDDCF

Enhanced DDC address detected.

This bit is set by hardware when the Enhanced

DDC address (60h/61h) is detected on the bus

while EDDCEN=1. It is cleared by hardware when

a Start or a Stop condition (STOPF=1) is detected,

or when the interface is disabled (PE=0).

0: No Enhanced DDC address detected on bus

1: Enhanced DDC address detected on bus

STOPF

BERR

EDDC

ST72734 数据表(PDF) 112 Page - STMicroelectronics

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