ST72734 datasheet(121/144 Pages) STMICROELECTRONICS

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ST72774/ST727754/ST72734

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PWM/BRM GENERATOR (Cont’d)

4.9.4 Register Description

4.9.4.1 PWM/BRM REGISTERS

On a channel basis, the 10 bits are separated into

two data registers:

– A 6-bit PWM register corresponding to the binary

weight of the PWM pulse.

– A 4-bit BRM register defining the intervals where

an incremental pulse is added to the beginning of

the original PWM pulse. Two BRM channel val-

ues share the same register.

Note: The number of PWM and BRM channels available

depends on the device. Refer to the device pin de-

scription and register map.

PWM[1:8] REGISTERS

Read/Write

Reset Value 1000 0000 (80h)

Bit 7 = Reserved (read as “1”)

Bit 6 = POL

Polarity Bit.

When POL is set, output signal polarity is inverse;

otherwise, no change occurs.

Bits 5:0 = P[5:0] PWM Pulse Binary Weight for

channel i .

BRM REGISTERS

BRM21 (Channels 2 + 1)

BRM43 (Channels 4 + 3)

BRM65 (Channels 6 + 5)

BRM87 (Channels 8 + 7)

Read/Write

Reset Value: 0000 0000 (00h)

Bits 7:4 = B[7:4]

BRM Bits (channel i+1)

Bits 3:0 = B[3:0]

BRM Bits (channel i)

4.9.4.2 OUTPUT ENABLE REGISTER

Read/Write

Reset Value 1000 0000 (80h)

Bit 7:0 = OE[7:0]

Output Enable Bit.

When OEi is set, PWM output function is enabled.

0: PWM output is disabled

1: PWM output is enabled

Note: From the programmer’s point of view, the PWM and

BRM registers can be regarded as being combined

to give one data value.

For example (10-bit)

Effective (with external RC filtering) DAC value

POL

OE7

OE6

OE5

OE4

OE3

OE2

OE1

OE0

POL

PPP

POL

PPPPP

PBBBB

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