ST72734 datasheet(124/144 Pages) STMICROELECTRONICS

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4.10.3.2 Digital A/D Conversion Result

The conversion is monotonic, meaning that the

result never decreases if the analog input does not

and never increases if the analog input does not.

If the input voltage (VAIN) is greater than or equal

to VDDA (high-level voltage reference) then the

conversion result in the DR register is FFh (full

scale) without overflow indication.

If input voltage (VAIN) is lower than or equal to

VSSA (low-level voltage reference) then the

conversion result in the DR register is 00h.

The A/D converter is linear and the digital result of

the conversion is stored in the ADCDR register.

The accuracy of the conversion is described in the

parametric section.

RAIN is the maximum recommended impedance

for an analog input signal. If the impedance is too

high, this will result in a loss of accuracy due to

leakage and sampling not being completed in the

alloted time.

4.10.3.3 A/D Conversion Phases

The A/D conversion is based on two conversion

phases as shown in Figure 77:

Sample capacitor loading [duration: tLOAD]

During this phase, the VAIN input voltage to be

measured is loaded into the CADC sample

capacitor.

A/D conversion [duration: tCONV]

During this phase, the A/D conversion is

computed (8 successive approximations cycles)

and the CADC sample capacitor is disconnected

from the analog input pin to get the optimum

analog to digital conversion accuracy.

While the ADC is on, these two phases are

continuously repeated.

At the end of each conversion, the sample

capacitor is kept

loaded

with

the

measurement

load.

The

advantage

this

behaviour

that

minimizes

the

current

consumption on the analog pin in case of single

input channel measurement.

4.10.3.4 Software Procedure

Refer to the control/status register (CSR) and data

Section 4.10.6 for the bit

definitions and to Figure 77 for the timings.

ADC Configuration

The total duration of the A/D conversion is 12 ADC

clock periods (1/fADC=4/fCPU).

The analog input ports must be configured as

input, no pull-up, no interrupt. Refer to the «I/O

ports» chapter. Using these pins as analog inputs

does not affect the ability of the port to be read as

a logic input.

In the CSR register:

– Select the CH[3:0] bits to assign the analog

channel to be converted.

ADC Conversion

In the CSR register:

– Set the ADON bit to enable the A/D converter

and to start the first conversion. From this time

on, the ADC performs a continuous conver-

sion of the selected channel.

When a conversion is complete

– The COCO bit is set by hardware.

– No interrupt is generated.

– The result is in the DR register and remains

valid until the next conversion has ended.

A write to the CSR register (with ADON set) aborts

the current conversion, resets the COCO bit and

starts a new conversion.

Figure 77. ADC Conversion Timings

4.10.4 Low Power Mode

Note: The A/D converter is disabled by resetting the

ADON bit. With this feature, power consumption is

reduced when no conversion is needed and be-

tween single shot conversions.

4.10.5 Interrupts

None

Mode

Description

WAIT

No effect on A/D Converter

ADCCSR WRITE

ADON

COCO BIT SET

tLOAD

tCONV

OPERATION

HOLD

CONTROL

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