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ST7LITEUS5 数据表(PDF) 108 Page - STMicroelectronics |
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ST7LITEUS5 数据表(HTML) 108 Page - STMicroelectronics |
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108 / 136 page  Obsolete Product(s) - Obsolete Product(s) Obsolete Product(s) - Obsolete Product(s) Electrical characteristics ST7LITEUS2, ST7LITEUS5 108/136 12.8 I/O port pin characteristics 12.8.1 General characteristics Subject to general operating conditions for VDD, fOSC, and TA unless otherwise specified. Figure 48. Two typical applications with unused I/O pin 1. Caution: During normal operation the ICCCLK pin must be pulled- up, internally or externally (external pull- up of 10k mandatory in noisy environment). This is to avoid entering I2C mode unexpectedly during a reset. 2. I/O can be left unconnected if it is configured as output (0 or 1) by the software. This has the advantage of greater EMC robustness and lower cost. Table 63. General characteristics Symbol Parameter Conditions Min Typ Max Unit VIL Input low level voltage -40°C to 125°C 0.3V DD V VIH Input high level voltage 0.7VDD Vhys Schmitt trigger voltage hysteresis(1) 1. Data based on characterization results, not tested in production. 400 mV IL Input leakage current VSS≤VIN≤VDD ±1 μA IS Static current consumption induced by each floating input pin(2) 2. Configuration not recommended, all unused pins must be kept at a fixed voltage: using the output mode of the I/O for example or an external pull-up or pull-down resistor (see Figure 48). Static peak current value taken at a fixed VIN value, based on design simulation and technology characteristics, not tested in production. This value depends on VDD and temperature values. Floating input mode 400 RPU Weak pull-up equivalent resistor(3) (4) 3. The RPU pull-up equivalent resistor is based on a resistive transistor (corresponding IPU current characteristics described in Figure 49). 4. RPU not applicable on PA3 because it is multiplexed on RESET pin VIN=VS S VDD=5 V 80 120 170 k Ω VDD=3 V 200(1) CIO I/O pin capacitance 5 pF tf(IO)out Output high to low level fall time 1) CL=50 pF Between 10% and 90% 25 ns tr(IO)out Output low to high level rise time 1) 25 tw(IT)in External interrupt pulse time(5) 5. To generate an external interrupt, a minimum pulse width has to be applied on an I/O port pin configured as an external interrupt source. 1tCPU 10k Ω UNUSED I/O PORT ST7XXX 10k Ω UNUSED I/O PORT ST7XXX VDD Obsolete Product(s) - Obsolete Product(s) |
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