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DS31256 数据表(PDF) 65 Page - Maxim Integrated Products

部件名 DS31256
功能描述  256-Channel, High-Throughput HDLC Controller
PDF  183 Pages
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制造商  MAXIM [Maxim Integrated Products]
网页  https://www.maximintegrated.com/en.html
标志 MAXIM - Maxim Integrated Products

DS31256 数据表(HTML) 65 Page - Maxim Integrated Products

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DS31256 256-Channel, High-Throughput HDLC Controller
65 of 183
Register Name:
BERTBC0
Register Description:
BERT 32-Bit Bit Counter (lower word)
Register Address:
0510h
Register Name:
BERTBC1
Register Description:
BERT 32-Bit Bit Counter (upper word)
Register Address:
0514h
BERTBC0: BERT Bit Counter 0 (lower word)
Bit #
7
6
5
4
3
2
1
0
Name
BERT 32-Bit Bit Counter (lower byte)
Default
0
0
0
0
0
0
0
0
Bit #
15
14
13
12
11
10
9
8
Name
BERT 32-Bit Bit Counter
Default
0
0
0
0
0
0
0
0
BERTBC1: BERT Bit Counter 0 (upper word)
Bit #
23
22
21
20
19
18
17
16
Name
BERT 32-Bit Bit Counter
Default
0
0
0
0
0
0
0
0
Bit #
31
30
29
28
27
26
25
24
Name
BERT 32-Bit Bit Counter (upper byte)
Default
0
0
0
0
0
0
0
0
Note: Bits that are underlined are read-only; all other bits are read-write
.
Bits 0 to 31/BERT 32-Bit Bit Counter (BERTBC0 and BERTBC1). This 32-bit counter increments for each
data bit (i.e., clock) received. This counter is not disabled when the receive BERT loses synchronization. This
counter is loaded with the current bit count value when the LC control bit in the BERTC0 register is toggled from
low (0) to high (1). When full, this counter saturates and sets the BBCO status bit.
Register Name:
BERTEC0
Register Description:
BERT 24-Bit Error Counter (lower) and Status Information
Register Address:
0518h
Bit #
7
6
5
4
3
2
1
0
Name
n/a
RA1
RA0
RLOS
BED
BBCO
BECO
SYNC
Default
0
0
0
0
0
0
0
0
Bit #
15
14
13
12
11
10
9
8
Name
BERT 24-Bit Error Counter (lower byte)
Default
0
0
0
0
0
0
0
0
Note: Bits that are underlined are read-only; all other bits are read-write.
Bit 0/Real-Time Synchronization Status (SYNC). Real-time status of the synchronizer (this bit is not latched). Is
set when the incoming pattern matches for 32 consecutive bit positions. Is cleared when six or more bits out of 64
are received in error.



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