DS31256 datasheet(22/183 Pages) MAXIM

22 / 183 page

DS31256 256-Channel, High-Throughput HDLC Controller

22 of 183

3.4 JTAG Signal Description

Signal Name:

JTCLK

Signal Description:

JTAG IEEE 1149.1 Test Serial Clock

Signal Type:

Input

This signal is used to shift data into JTDI on the rising edge and out of JTDO on the falling edge. If unused, this

signal should be pulled high.

Signal Name:

JTDI

Signal Description:

JTAG IEEE 1149.1 Test Serial-Data Input

Signal Type:

Input (with internal 10k

W pullup)

Test instructions and data are clocked into this signal on the rising edge of JTCLK. If unused, this signal should be

pulled high. This signal has an internal pullup.

Signal Name:

JTDO

Signal Description:

JTAG IEEE 1149.1 Test Serial-Data Output

Signal Type:

Output

Test instructions are clocked out of this signal on the falling edge of JTCLK. If unused, this signal should be left

open circuited.

Signal Name:

JTRST

Signal Description:

JTAG IEEE 1149.1 Test Reset

Signal Type:

Input (with internal 10k

W pullup)

This signal is used to asynchronously reset the test access port controller. At power-up,

JTRST must be set low

and then high. This action sets the device into the boundary scan bypass mode, allowing normal device operation.

If boundary scan is not used, this signal should be held low. This signal has an internal pullup.

Signal Name:

JTMS

Signal Description:

JTAG IEEE 1149.1 Test Mode Select

Signal Type:

Input (with internal 10k

W pullup)

This signal is sampled on the rising edge of JTCLK and is used to place the test port into the various defined IEEE

1149.1 states. If unused, this signal should be pulled high. This signal has an internal pullup.

3.5 PCI Bus Signal Description

Signal Name:

PCLK

Signal Description:

PCI and System Clock

Signal Type:

Input (Schmitt triggered)

This clock input provides timing for the PCI bus and the device’s internal logic. A 25MHz to 33MHz clock with a

nominal 50% duty cycle should be applied here.

Signal Name:

PRST

Signal Description:

PCI Reset

Signal Type:

Input

This active-low input is used to force an asynchronous reset to both the PCI bus and the device’s internal logic.

When forced low, this input forces all the internal logic of the device into its default state, forces the PCI outputs

into tri-state, and forces the TD[15:0] output port-data signals high.

Signal Name:

PAD0 to PAD31

Signal Description:

PCI Address and Data Multiplexed Bus

Signal Type:

Input/Output (tri-state capable)

Both address and data information are multiplexed onto these signals. Each bus transaction consists of an address

phase followed by one or more data phases. Data can be either read or written in bursts. The address is transferred

during the first clock cycle of a bus transaction. When the Little Endian format is selected, PAD[31:24] is the

MSB of the DWORD; when Big Endian is selected, PAD[7:0] contains the MSB. When the device is an initiator,

DS31256 数据表(PDF) 22 Page - Maxim Integrated Products

DS31256 数据表(HTML) 22 Page - Maxim Integrated Products

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载

链接网址

DS31256 数据表(PDF) 22 Page - Maxim Integrated Products

DS31256 数据表(HTML) 22 Page - Maxim Integrated Products

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表 下载

链接网址

数据表下载