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DS31256 数据表(PDF) 46 Page - Maxim Integrated Products |
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DS31256 数据表(HTML) 46 Page - Maxim Integrated Products |
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46 / 183 page ![]() DS31256 256-Channel, High-Throughput HDLC Controller 46 of 183 Figure 6-1. Layer 1 Block Diagram RS RC RD SLOW HDLC (One per Port) FAST HDLC Layer 1 State Machine Receive Transmit Channel- ized Local Loop- Back (CLLB) Channel- ized Network Loop- Back (CNLB) V.54 Detector PORT RAM (see Sec. 5.3) Invert Clock / Data / Sync Local Loop- Back (LLB) Invert Clock / Data / Sync Force All Ones TC TD TS Over- Sample with PCLK Un- Channel- ized Network Loopback (UNLB) Over- Sample with PCLK BERT/ Fast HDLC Mux BERT Mux (Figure 6-7) 1 of 16 LLB UNLB Ports 0, 1, 2 Only To / From FIFO Block l1_bd Ports 0 & 1 Only |
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