DS31256 datasheet(83/183 Pages) MAXIM

83 / 183 page

DS31256 256-Channel, High-Throughput HDLC Controller

83 of 183

9. DMA

9.1 Introduction

The DMA block (Figure 2-1) handles the transfer of packet data from the FIFO block to the PCI block

and vice versa. Throughout this section, the terms host and descriptor are used. Host is defined as the

CPU or intelligent controller that sits on the PCI bus and instructs the device about how to handle the

incoming and outgoing packet data. Descriptor is defined as a preformatted message that is passed from

the host to the DMA block or vice versa to indicate where packet data should be placed or obtained from.

On power-up, the DMA is disabled because the RDE and TDE control bits in the master configuration

in Table 9-A (which includes all 256 channel locations in the receive and transmit configuration RAMs),

then enable the DMA by setting to the RDE and TDE control bits to 1.

The structure of the DMA is such that the receive- and transmit-side descriptor-address spaces can be

shared, even among multiple chips on the same bus. Through the master control register, the host

determines how long the DMA is allowed to burst onto the PCI bus. The default value is 32 dwords (128

Bytes) but, through the DT0 and DT1 control bits, the host can enable the receive or transmit DMAs to

burst either 64 dwords (256 Bytes), 128 dwords (512 Bytes), or 256 dwords (1024 Bytes).

The receive and transmit packet descriptors have almost identical structures (Sections 9.2.2 and 9.3.2),

which provide a minimal amount of host intervention in store-and-forward applications. In other words,

the receive descriptors created by the receive DMA can be used directly by the transmit DMA. The

receive and transmit portions of the DMA are completely independent and are discussed separately.

The DS31256 has no restrictions on the transmit side, but has the following restrictions on the location

and size of receive buffers in host memory:

· All receive buffers must start on a DWORD aligned address.

· All receive buffers must have a size in bytes that is a multiple of 4.

DS31256 数据表(PDF) 83 Page - Maxim Integrated Products