DS31256 datasheet(58/183 Pages) MAXIM

部件名	DS31256

功能描述	256-Channel, High-Throughput HDLC Controller

PDF	183 Pages

Scroll/Zoom	100%

制造商	MAXIM [Maxim Integrated Products]

网页	https://www.maximintegrated.com/en.html

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58 / 183 page

DS31256 256-Channel, High-Throughput HDLC Controller

58 of 183

Figure 6-5. Receive V.54 Host Algorithm

Set Up the

DS0 Channel

Toggle VRST

Wait for

SLBP = 1

VTO = 1?

Place DS0

Channels into

Loopback

Yes

Wait for

SLBP = 1

Take DS0

Channels out

of Loopback

v54host

SLBP is a status bit that is reported

in the SV54 register (Section 5.3)

VRST is a control bit that is in the Receive

Port Control Register (Section 6.2)

VTO is a status bit that is in the Receive

Port Control Register (Section 6.2)

SLBP is a status bit that is reported

in the SV54 register (Section 5.3)

DS0 channels can be configured to search

for the V.54 loop pattern via the Receive

Layer 1 Configuration Register (Section 6.3)

NOTES

ALGORITHM

DS0 channels can be placed into loopback

via the Receive Layer 1 Configuration Register

(Section 6.3)

DS0 channels can be taken out of loopback

via the Receive Layer 1 Configuration Register

(Section 6.3)

DS31256 数据表(PDF) 58 Page - Maxim Integrated Products

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