DS31256 datasheet(6/183 Pages) MAXIM

6 / 183 page

DS31256 256-Channel, High-Throughput HDLC Controller

6 of 183

1. MAIN FEATUERS

§ Layer 1

Can simultaneously support up to 60 T1 or 64 E1

data streams, or two T3 data streams

16 independent physical ports capable of speeds

up to 10MHz; three ports are also capable of

speeds up to 52MHz

Each port can be independently configured for

either channelized or unchannelized

operation

Each physical channelized port can handle one,

two, or four T1 or E1 data streams

Supports N x 64kbps and N x 56kbps

On-board V.54 loopback detector

On-board BERT generation and detection

Per DS0 channel loopback in both directions

Unchannelized loopbacks in both directions

§ HDLC

256 independent channels

Up to 132Mbps throughput in both the receive

and transmit directions

Transparent mode

Three fast HDLC controllers capable of

operating up to 52 MHz

Automatic flag detection and generation

Shared opening and closing flag

Interfame fill

Zero stuffing and destuffing

CRC16/32 checking and generation

Abort detection and generation

CRC error and long/short frame error detection

Invert clock

Invert data

§ FIFO

Large 16kB receive and 16kB transmit buffers

maximize PCI bus efficiency

Small block size of 16 Bytes allows maximum

flexibility

Programmable low and high watermarks

Programmable HDLC channel priority setting

§ DMA

Efficient scatter-gather DMA minimizes system

memory utilization

Programmable small and large buffer sizes up to

8188 Bytes and algorithm select

Descriptor bursting to conserve PCI bus

bandwidth

Identical receive and transmit descriptors

minimize host processing in store-and-

forward

Automatic channel disabling and enabling on

transmit errors

Receive packets are timestamped

Transmit packet priority setting

§ PCI Bus

32-bit, 33MHz

Version 2.1 Compliant

Contains extension signals that allow adoption to

custom buses

Can burst up to 256 32-bit words to maximize

bus efficiency

§ Local Bus

Can be bridged from the PCI bus to simplify

system design, or a configuration bus

Can arbitrate for the bus when in bridge mode

Configurable as 8 or 16 bits wide

Supports a 1MB address space when in bridge

mode

Supports Intel and Motorola bus timing

§ JTAG Test Access

§ 3.3V low-power CMOS with 5V tolerant I/Os

§ 256-pin plastic BGA package (27mm x 27mm)

Governing Specifications

The DS31256 fully meets the following specifications:

· ANSI (American National Standards Institute) T1.403-1995 Network-to-Customer Installation DS1 Metallic

Interface March 21, 1995

· PCI Local Bus Specification V2.1 June 1, 1995

· ITU Q.921 March 1993

· ISO Standard 3309-1979 Data Communications–HDLC Procedures–Frame Structure

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