DS31256 datasheet(48/183 Pages) MAXIM

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DS31256 256-Channel, High-Throughput HDLC Controller

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6.2 Port Register Descriptions

Receive-Side Control Bits (one each for all 16 ports)

RP[n]CR, where n = 0 to 15 for each port

Receive Port [n] Control Register

See the Register Map in Section 4.

Bit #

Name

RSS1

RSS0

RSD1

RSD0

VRST

RISE

RIDE

RICE

Default

Bit #

Name

RCOFA

IERC

VLB

VTO

n/a

LLB

RUEN

RP[i]HS

Default

Note: Bits that are underlined are read-only; all other bits are read-write.

Bit 0/Invert Clock Enable (RICE)

0 = do not invert clock (normal mode)

1 = invert clock (inverted clock mode)

Bit 1/Invert Data Enable (RIDE)

0 = do not invert data (normal mode)

1 = invert data (inverted data mode)

Bit 2/Invert Sync Enable (RISE)

0 = do not invert sync pulse (normal mode)

1 = invert sync pulse (inverted sync pulse mode)

Bit 3/V.54 Detector Reset (VRST). Toggling this bit from 0 to 1 and then back to 0 causes the internal V.54

detector to be reset and begin searching for the V.54 loop-up pattern. See Section 6.4 for more details.

Bit 4/Sync Delay Bit 0 (RSD0); Bit 5/Sync Delay Bit 1 (RSD1). These two bits define the format of the sync

signal that is applied to the RS[n] input. These bits are ignored if the port has been configured to operate in an

unchannelized fashion (RUEN = 1).

00 = sync pulse is 0 clocks early

01 = sync pulse is 1/2 clock early

10 = sync pulse is 1 clock early

11 = sync pulse is 2 clocks early

Bit 6/Sync Select Bit 0 (RSS0); Bit 7/Sync Select Bit 1 (RSS1). These two bits select the mode in which each

port is to be operated. Each port can be configured to accept 24, 32, 64, or 128 DS0 channels at an 8kHz rate.

These bits are ignored if the port has been configured to operate in an unchannelized fashion (RUEN = 1).

00 = T1 Mode (24 DS0 channels and 193 RC clocks between RS sync signals)

01 = E1 Mode (32 DS0 channels and 256 RC clocks between RS sync signals)

10 = 4.096MHz Mode (64 DS0 channels and 512 RC clocks between RS sync signals)

11 = 8.192MHz Mode (128 DS0 channels and 1024 RC clocks between RS sync signals)

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