DS31256 datasheet(97/183 Pages) MAXIM

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DS31256 256-Channel, High-Throughput HDLC Controller

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9.2.4 Done Queue

The DMA writes to the receive done queue when it has filled a free data buffer with packet data and has

loaded the associated packet descriptor with all the necessary information. The descriptor location is

indicated through a 16-bit pointer that the host uses with the receive descriptor base address to find the

exact 32-bit address of the associated receive descriptor.

Figure 9-7. Receive Done-Queue Descriptor

dword 0

EOF

Status(3)

BUFCNT(3)

HDLC Channel (8)

Descriptor Pointer (16)

Note 1: The organization of the done queue is not affected by the enabling of Big Endian.

Note 2: Descriptor pointer is an index, not an absolute address.

dword 0; Bits 0 to 15/Descriptor Pointer. This 16-bit value is the offset from the receive descriptor base

address of a receive packet descriptor that has been readied by the DMA and is available for the host to begin

processing. Note: This is an index, not an absolute address.

dword 0; Bits 16 to 23/HDLC Channel Number. This is an HDLC channel number, which can be from 1 to

256.

00000000 (00h) = HDLC channel number 1

11111111 (FFh) = HDLC channel number 256

dword 0; Bits 24 to 26/Buffer Count (BUFCNT). If an HDLC channel has been configured to only write to

the done queue after a packet has been completely received (i.e., the threshold field in the receive DMA

configuration RAM is set to 000), then BUFCNT is always set to 000. If the HDLC channel has been

configured through the threshold field to write to the done queue after a programmable number of buffers

(from 1 to 7) has been filled, then BUFCNT corresponds to the number of buffers that have been written to

host memory. The BUFCNT is less than the threshold field value when the incoming packet does not require

the number of buffers specified in the threshold field.

000 = indicates that a complete packet has been received (only used when threshold = 000)

001 = 1 buffer has been filled

010 = 2 buffers have been filled

111 = 7 buffers have been filled

dword 0; Bits 27 to 29/Packet Status. These three bits report the final status of an incoming packet. They are

only valid when the EOF bit is set to 1 (EOF = 1).

000 = no error, valid packet received

001 = receive FIFO overflow (remainder of the packet discarded)

010 = CRC checksum error

011 = HDLC frame abort sequence detected (remainder of the packet discarded)

100 = nonaligned byte count error (not an integral number of bytes)

101 = long frame abort (max packet length exceeded; remainder of the packet discarded)

110 = PCI abort (remainder of the packet discarded)

111 = reserved state (never occurs in normal device operation)

dword 0; Bit 30/End of Frame (EOF). This bit is set to 1 when this receive descriptor is the last one in the

current descriptor chain. This indicates that a packet has been fully received or an error has been detected,

which has caused a premature termination.

dword 0; Bit 31/Valid Done-Queue Descriptor (V). This bit is set to 0 by the receive DMA. Instead of

reading the receive done-queue read pointer to locate completed done-queue descriptors, the host can use this

bit, since the DMA sets the bit to 0 when it is written into the queue. If the latter scheme is used, the host must

set this bit to 1 when the done queue descriptor is read.

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