DS31256 datasheet(74/183 Pages) MAXIM

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DS31256 256-Channel, High-Throughput HDLC Controller

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8. FIFO

8.1 General Description and Example

The DS31256 contains one 16kB FIFO for the receive path and another 16kB FIFO for the transmit path.

Both of these FIFOs are organized into blocks. Since a block is defined as 4 dwords (16 Bytes), each

FIFO is made up of 1024 blocks. Figure 8-1 shows an FIFO example.

The FIFO contains a state machine that is constantly polling the 16 ports to determine if any data is ready

for transfer to/from the FIFO from/to the HDLC engines. The 16 ports are priority decoded with port 0

getting the highest priority and port 15 getting the lowest priority. Therefore, all the enabled HDLC

channels on the lower numbered ports are serviced before the higher numbered ports. As long as the

maximum throughput rate of 132Mbps is not exceeded, the DS31256 ensures there is enough bandwidth

in this transfer to prevent any data loss between the HDLC engines and the FIFO.

The FIFO also controls which HDLC channel the DMA should service to read data out of the FIFO on

the receive side and to write data into the FIFO on the transmit side. Which channel gets the highest

priority from the FIFO is configurable through some control bits in the master configuration register

(Section 5.2). There are two control bits for the receive side (RFPC0 and RFPC1) and two control bits

for the transmit side (TFPC0 and TFPC1) that determine the priority algorithm as shown in Table 8-A.

Table 8-A. FIFO Priority Algorithm Select

OPTION

HDLC CHANNELS THAT ARE

PRIORITY DECODED

HDLC CHANNELS THAT ARE SERVICED

ROUND ROBIN

None

1 to 256

1 to 3

4 to 256

16 to 1

17 to 256

64 to 1

65 to 256

To maintain maximum flexibility for channel reconfiguration, each block within the FIFO can be

assigned to any of the 256 HDLC channels. Also, blocks are link-listed together to form a chain whereby

each block points to the next block in the chain. The minimum size of the link-listed chain is 4 blocks

(64 Bytes) and the maximum is the full size of the FIFO, which is 1024 blocks.

To assign a set of blocks to a particular HDLC channel, the host must configure the starting block pointer

and the block pointer RAM. The starting block pointer assigns a particular HDLC channel to a set of

link-listed blocks by pointing to one of the blocks within the chain (it does not matter which block in the

chain is pointed to). The block pointer RAM must be configured for each block that is being used within

the FIFO. The block pointer RAM indicates the next block in the link-listed chain.

Figure 8-1 shows an example of how to configure the starting block pointer and the block pointer RAM.

In this example, only three HDLC channels are being used (channels 2, 6, and 16). The device knows

that channel 2 has been assigned to the eight link-listed blocks of 112, 118, 119, 120, 121, 122, 125, and

126 because a block pointer of 125 has been programmed into the channel 2 position of the starting

block pointer. The block pointer RAM tells the device how to link the eight blocks together to form a

circular chain.

The host must set the watermarks for the receive and transmit paths. The receive path has a high

watermark and the transmit path has a low watermark.

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