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DS31256 256-Channel, High-Throughput HDLC Controller

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5.3.2 Status and Interrupt Register Description

Status Master Register

0020h

Bit #

Name

n/a

PPERR

PSERR

SBERT

STCOFA

SRCOFA

Default

Bit #

Name

LBINT

LBE

n/a

Default

Note: Bits that are underlined are read-only; all other bits are read-write.

Bit 0/Status Bit for Change-of-Frame Alignment (SRCOFA). This status bit is set to 1 if one or more of the

receive ports has experienced a COFA event. The host must read the RCOFA bit in the receive port control

registers (RP[n]CR) of each active port to determine which port or ports has seen the COFA. The SRCOFA bit is

cleared when read and is not set again until the one or more receive ports has experienced another COFA. If

enabled through the SRCOFA bit in the interrupt mask for SM (ISM), the setting of this bit causes a hardware

interrupt at the PCI bus through the

PINTA signal pin and also at the LINT if the local bus is in configuration

mode.

Bit 1/Status Bit for Transmit Change-of-Frame Alignment (STCOFA). This status bit is set to 1 if one or more

of the transmit ports has experienced a COFA event. The host must read the TCOFA bit in the transmit port

control registers (TP[n]CR) of each active port to determine which port or ports has seen the COFA. The STCOFA

bit is cleared when read and is not set again until one or more transmit ports has experienced another COFA. If

enabled through the STCOFA bit in the ISM, the setting of this bit causes a hardware interrupt at the PCI bus

through the

PINTA signal pin and also at the LINT if the local bus is in configuration mode.

Bit 2/Status Bit for Change of State in BERT (SBERT). This status bit is set to 1 if there is a major change of

state in the BERT receiver. A major change of state is defined as either a change in the receive synchronization

(i.e., the BERT has gone into or out of receive synchronization), a bit error has been detected, or an overflow has

occurred in either the bit counter or the error counter. The host must read the status bits of the BERT in the BERT

status register (BERTEC0) to determine the change of state. The SBERT bit is cleared when read and is not set

again until the BERT has experienced another change of state. If enabled through the SBERT bit in the ISM, the

setting of this bit causees a hardware interrupt at the PCI bus through the

PINTA signal pin and also at the LINT if

the local bus is in configuration mode.

Bit 3/Status Bit for PCI System Error (PSERR). This status bit is a software version of the PCI bus hardware

pin PSERR. It is set to 1 if the PCI bus detects an address parity error or other PCI bus error. The PSERR bit is

cleared when read and is not set again until another PCI bus error has occurred. If enabled through the PSERR bit

in the ISM, the setting of this bit causes a hardware interrupt at the PCI bus through the

PINTA signal pin and also

at the

LINT if the local bus is in configuration mode. This status bit is also reported in the control/status register in

the PCI configuration registers (Section 10).

Bit 4/Status Bit for PCI System Error (PPERR). This status bit is a software version of the PCI bus hardware

pin PPERR. It is set to 1 if the PCI bus detects parity errors on the PAD and

PCBE buses as experienced or

reported by a target. The PPERR bit is cleared when read and is not set again until another parity error has been

detected. If enabled through the PPERR bit in the interrupt mask for SM (ISM), the setting of this bit causes a

hardware interrupt at the PCI bus through the

PINTA signal pin and also at the LINT if the local bus is in

configuration mode. This status bit is also reported in the control/status register in the PCI configuration registers

(Section 10).

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